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Service Value Aware Memory Scheduler by Estimating Request Weight and Using per-Thread Traffic Lights

Keisuke Kuroyanagi 1 André Seznec 2 
2 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : The memory controller has become one of the performance enabler of a computer system. Its impact is even higher on multicores than it was on uniprocessor systems. In this paper, we propose the sErvice Value Aware memory scheduler (EVA) to enhance memory usage. EVA builds on two concepts, the request weight and the per-thread traffic light. For a read request on memory, the request weight is an evaluation of the work allowed by the request. Per-thread traffic lights are used to track whether or not in a given situation it is worth to service requests from a thread, e.g. if a given thread is blocked by refreshing on a rank then it is not worth to serve requests from the same thread on another rank. The EVA scheduler bases its scheduling decision on a service value which is heuristically computed using the request weight and per-thread traffic lights. Our EVA scheduler implementation relies on several hardware mechanisms, a request weight estimator, per-thread traffic estimators and a next row predictor. Using these components, our EVA scheduler estimates scores to issue scheduling decisions. EVA is shown to perform efficiently and fairly compared with previous proposed memory schedulers. For the memory scheduling competition, we submit EVA to Delay and PFP tracks and EVA-E (EVA with optimisations for EDP) to EDP track. Total delay is 2975 ×107, EDP value is 19.79 and PFP value is 2842 ×107.
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Submitted on : Tuesday, October 30, 2012 - 10:42:00 AM
Last modification on : Tuesday, July 5, 2022 - 8:38:21 AM
Long-term archiving on: : Thursday, January 31, 2013 - 3:45:39 AM


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  • HAL Id : hal-00746951, version 1


Keisuke Kuroyanagi, André Seznec. Service Value Aware Memory Scheduler by Estimating Request Weight and Using per-Thread Traffic Lights. 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC), Rajeev Balasubramonian (Univ. of Utah), Niladrish Chatterjee (Univ. of Utah), Zeshan Chishti (Intel), Jun 2012, Portland, United States. ⟨hal-00746951⟩



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