Spatio-Temporal Scheduling for 3D Reconfigurable \& Multiprocessor Architecture

Abstract : This article proposes a spatio-temporal schedul- ing algorithm for a three-dimensional integrated circuits (3D ICs) defined by stacking an homogeneous embedded Field- Programmable Gate Array (eFPGA) above an homogenous Chip MultiProcessor (CMP) layer over through-silicon vias (TSVs) connection. Our proposal, based on Proportionate-fair (Pfair) algorithm, computes the spatio-temporal scheduling of hardware tasks on the reconfigurable resources by taking into account the communication between tasks and then places the associated software tasks on the multiprocessors layer. Compared to the "equivalent" solutions produced by the recursive Branch and Bound (BB) algorithm, our proposal shows up to 14,5% communication cost reduction.
Type de document :
Communication dans un congrès
International Design and Test Symposium, IDT 2012, Dec 2012, Doha, Qatar. 2012
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https://hal.inria.fr/hal-00753902
Contributeur : Daniel Chillet <>
Soumis le : lundi 19 novembre 2012 - 18:13:57
Dernière modification le : mercredi 11 avril 2018 - 02:01:25

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  • HAL Id : hal-00753902, version 1

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Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Sébastien Pillement. Spatio-Temporal Scheduling for 3D Reconfigurable \& Multiprocessor Architecture. International Design and Test Symposium, IDT 2012, Dec 2012, Doha, Qatar. 2012. 〈hal-00753902〉

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