Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems, vol.6, issue.2, pp.149-206, 2001. ,
DOI : 10.1145/375977.375978
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.59.2118
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis , CODES+ISSS '07, pp.9-14, 2007. ,
DOI : 10.1145/1289816.1289823
Milan: A model based integrated simulation framework for desgin of embedded suystems, LCTES, pp.82-87, 2001. ,
Metropolis: an integrated electronic system design environment, Computer, vol.36, issue.4, pp.45-52, 2003. ,
DOI : 10.1109/MC.2003.1193228
Pico-npa: High-level synthesis of nonprogrammable hardware accelerators, The Journal of VLSI Signal Processing, vol.31, issue.2, pp.127-142, 2002. ,
DOI : 10.1023/A:1015341305426
A transformationbased method for loop folding, IEEE Trans. on CAD of Integrated Circuits and Systems, pp.439-450, 1994. ,
Elimination of redundant memory traffic in high-level synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.15, issue.11, pp.1354-1363, 1996. ,
DOI : 10.1109/43.543768
Performance and area modeling of complete FPGA designs in the presence of loop transformations, IEEE Transactions on Computers, vol.53, issue.11, pp.1420-1435, 2004. ,
DOI : 10.1109/TC.2004.101
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations, 16th International Conference on VLSI Design, 2003. Proceedings., 2003. ,
DOI : 10.1109/ICVD.2003.1183177
Incremental hierarchical memory size estimation for steering of loop transformations, ACM Transactions on Design Automation of Electronic Systems, vol.12, issue.4, 2007. ,
DOI : 10.1145/1278349.1278363
MPSoC memory optimization using program transformation, ACM Transactions on Design Automation of Electronic Systems, vol.12, issue.4, 2007. ,
DOI : 10.1145/1278349.1278356
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification, Journal of Signal Processing Systems, vol.12, issue.3, pp.193-213, 2010. ,
DOI : 10.1007/s11265-009-0351-6
The JPEG still picture compression standard, Communications of the ACM, vol.34, issue.4, pp.30-44, 1991. ,
DOI : 10.1145/103085.103089
N-synchronous kahn networks: a relaxed model of synchrony for real-time systems, Proc. of the ACM SIGPLAN-SIGACT symposium on Principles of programming languages (POPL '06) ,
Abstract clocks for the dse of dataintensive applications on mpsocs, ISPA 2012 4th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00758165
Opt4J -A Modular Framework for Meta-heuristic Optimization, Proc. of the Genetic and Evolutionary Computing Conference, 2011. ,
Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications, Journal of Systems Architecture, vol.57, issue.9, pp.815-829, 2011. ,
DOI : 10.1016/j.sysarc.2010.12.002
URL : https://hal.archives-ouvertes.fr/inria-00605069
Multidimensional synchronous dataflow, IEEE Transactions on Signal Processing, vol.50, issue.8, pp.2064-2079, 2002. ,
DOI : 10.1109/TSP.2002.800830
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops, 2012 International Conference on Embedded Computer Systems (SAMOS), 2012. ,
DOI : 10.1109/SAMOS.2012.6404166
URL : https://hal.archives-ouvertes.fr/hal-00758159
Performance assessment of multiobjective optimizers: an analysis and review, IEEE Transactions on Evolutionary Computation, vol.7, issue.2, pp.117-132, 2003. ,
DOI : 10.1109/TEVC.2003.810758