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CLASSY: a clock analysis system for rapid prototyping of embedded applications on MPSoCs

Xin An 1 Sarra Boumedien 2 Abdoulaye Gamatié 2 Eric Rutten 1 
1 SARDES - System architecture for reflective distributed computing environments
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
2 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : This paper presents an abstract multi-clock oriented reasoning for the rapid prototyping of embedded applications executed on multiprocessor systems-on-chip (MPSoCs). The scheduling of applications on execution platforms composed of processors operating at various frequencies is described and analyzed with clocks. As in the static scheduling of synchronous dataflows (SDFs), requirements for admissible schedules are investigated, which come not only from expected application behavior, but also from execution platform. An algorithm is proposed to construct admissible schedules respecting identified requirements. It is then adapted to synthesize admissible schedules for adaptive system behaviors. The modeling, analysis and algorithms presented in this paper have been implemented in a prototype tool named CLASSY (standing for CLock AnalySis SYstem).
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Contributor : Abdoulaye Gamatié Connect in order to contact the contributor
Submitted on : Wednesday, November 28, 2012 - 11:59:32 AM
Last modification on : Tuesday, July 26, 2022 - 3:49:25 AM



Xin An, Sarra Boumedien, Abdoulaye Gamatié, Eric Rutten. CLASSY: a clock analysis system for rapid prototyping of embedded applications on MPSoCs. Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems, May 2012, St. Goar, Germany. pp.3--12, ⟨10.1145/2236576.2236577⟩. ⟨hal-00758194⟩



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