Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA

Christophe Alias 1, * Alain Darte 1, * Alexandru Plesco 1
* Corresponding author
1 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : In the context of the high-level synthesis (HLS) of regular kernels offloaded to FPGA and communicating with an external DDR memory, we show how to automatically generate adequate communicating processes for optimizing the transfer of remote data. This requires a generalized form of communication coalescing where data can be transferred from the external memory even when this memory is not fully up-to-date. Experiments with Altera HLS tools demonstrate that this automatization, based on advanced polyhedral code analysis and code generation techniques, can be used to efficiently map C kernels to FPGA, by generating, entirely at C level, all the necessary glue (the communication processes), which is compiled with the same HLS tool as for the computation kernel.
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Conference papers
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https://hal.inria.fr/hal-00761473
Contributor : Alain Darte <>
Submitted on : Wednesday, December 5, 2012 - 3:28:24 PM
Last modification on : Saturday, April 21, 2018 - 1:27:16 AM

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Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA. 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), Feb 2012, New Orleans, United States. pp.285--286, ⟨10.1145/2145816.2145856⟩. ⟨hal-00761473⟩

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