Abstract : The UML (Unified Modeling Language) Profile for Modeling and Analysis of Real-Time and Embedded (MARTE) systems promises a general modeling framework to design and analyze embedded systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on verification techniques supported. The Clock Constraint Specification Language (CCSL) has been defined in an annex of MARTE precisely to address semantic issues on time and causal aspects in relation with MARTE models. In the context of System-on-Chip design, some early work was proposed to use CCSL as a high-level specification language from which an observation network could be built. That observation network was used to observe early prototype implementations of the system under design and verify its compliance with respect to the CCSL specification. The proposed approach consisted in manually building a library of observer nodes for each CCSL operator and defining a generic mechanism to compose these nodes. This paper introduces a technique to generate a complete observer directly from a CCSL specification without requiring the manual construction of a library. The technique relies on a new state-based semantics given to a selected subset of CCSL operators. The study focuses specifically on boundedness issues with some CCSL operators that were previously artificially bounded to allow for exhaustive analyses.