Generation of Executable Representation for Processor Simulation with Dynamic Translation

Jiajia Song 1 Claude Helmstetter 1 Vania Joloboff 1 Hongwei Hao 2
1 FORMES - Formal Methods for Embedded Systems
LIAMA - Laboratoire Franco-Chinois d'Informatique, d'Automatique et de Mathématiques Appliquées, Inria Paris-Rocquencourt
2 USTB - University of Science and Technology Beijing [Beijing]
Abstract : Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive simulation, static translation and dynamic translation. This paper presents a simulator where we have developed and integrated three techniques: an interpretive simulator and two variants of dynamic translation. In the third variant, the simulator caches an intermediate representation that consists of pseudo instructions. These pseudo instructions use semantic functions that can be specialized using partial evaluation technique and a code generator. These three methods have been used to run the same simulated programs and compare their performance. The experiments show that the partial evaluation technique increases performance and flexibility, but also shows that it may have adverse effects.
Type de document :
Communication dans un congrès
IEEE. 2008 International Conference on Computer Science and Software Engineering, Dec 2008, Wuhan, China. IEEE, 2008, 〈10.1109/CSSE.2008.635〉
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https://hal.inria.fr/hal-00777157
Contributeur : Vania Joloboff <>
Soumis le : jeudi 17 janvier 2013 - 03:51:52
Dernière modification le : mardi 17 avril 2018 - 11:25:20

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Jiajia Song, Claude Helmstetter, Vania Joloboff, Hongwei Hao. Generation of Executable Representation for Processor Simulation with Dynamic Translation. IEEE. 2008 International Conference on Computer Science and Software Engineering, Dec 2008, Wuhan, China. IEEE, 2008, 〈10.1109/CSSE.2008.635〉. 〈hal-00777157〉

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