K. Apt and D. Kozen, Limits for automatic verification of finite-state concurrent systems, Information Processing Letters, vol.22, issue.6, pp.307-309, 1986.
DOI : 10.1016/0020-0190(86)90071-2

J. Barnat, L. Brim, M. Ce?ka, and P. Ro?kai, DiVinE : Parallel Distributed Model Checker (Tool paper), HiBi/PDMC, pp.4-7, 2010.
DOI : 10.1109/pdmc-hibi.2010.9

K. Baukus, Y. Lakhnech, and K. Stahl, Parameterized Verification of a Cache Coherence Protocol: Safety and Liveness, VMCAI, pp.317-330, 2002.
DOI : 10.1007/3-540-47813-2_22

R. E. Bryant, S. K. Lahiri, and S. A. Seshia, Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions, CAV, pp.78-92, 2002.
DOI : 10.1007/3-540-45657-0_7

C. Chou, P. Mannava, and S. Park, A Simple Method for Parameterized Verification of Cache Coherence Protocols, FMCAD, pp.382-398, 2004.
DOI : 10.1007/978-3-540-30494-4_27

A. Cimatti, E. Clarke, E. Giunchiglia, F. Giunchiglia, M. Pistore et al., NuSMV 2: An OpenSource Tool for Symbolic Model Checking, CAV, pp.241-268, 2002.
DOI : 10.1007/3-540-45657-0_29

E. Sylvain-conchon, J. Contejean, S. Kanig, and . Lescuyer, CC(X) : Semantic combination of congruence closure with solvable theories, ENTCS, vol.198, issue.2, pp.51-69, 2008.

S. Conchon and J. Filliâtre, Type-Safe Modular Hash-Consing, In ACM SIGPLAN Workshop on ML, 2006.

A. Sylvain-conchon, S. Goel, A. Krsti´ckrsti´c, F. Mebsout, and . Za¨?diza¨?di, Cubicle : A parallel SMT-based model checker for parameterized systems, CAV, pp.718-724

D. L. Dill, A. J. Drexler, A. J. Hu, and C. Yang, Protocol verification as a hardware design aid, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp.522-525, 1992.
DOI : 10.1109/ICCD.1992.276232

J. Filliâtre and K. Kalyanasundaram, Functory: A Distributed Computing Library for Objective Caml, TFP, pp.65-81, 2011.
DOI : 10.1007/978-3-642-32037-8_5

S. Ghilardi, E. Nicolini, S. Ranise, and D. Zucchelli, Towards SMT Model Checking of Array-Based Systems, IJCAR, pp.67-82, 2008.
DOI : 10.1007/978-3-540-71070-7_6
URL : https://hal.archives-ouvertes.fr/inria-00576600

S. Ghilardi and S. Ranise, Backward Reachability of Array-based Systems by SMT solving: Termination and Invariant Synthesis, Logical Methods in Computer Science, vol.6, issue.4, 2010.
DOI : 10.2168/LMCS-6(4:10)2010

S. Ghilardi and S. Ranise, MCMT: A Model Checker Modulo Theories, IJCAR, pp.22-29, 2010.
DOI : 10.1007/978-3-642-14203-1_3

O. Grumberg, T. Heyman, N. Ifergan, and A. Schuster, Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation, CHARME, pp.129-145, 2005.
DOI : 10.1007/11560548_12

K. Havelund and T. Pressburger, Model checking JAVA programs using JAVA PathFinder, International Journal on Software Tools for Technology Transfer (STTT), vol.2, issue.4, pp.366-381, 2000.
DOI : 10.1007/s100090050043
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.29.7274

T. Henzinger, R. Jhala, R. Majumdar, and G. Sutre, Software Verification with BLAST, Model Checking Software, pp.624-624, 2003.
DOI : 10.1007/3-540-44829-2_17
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.6477

G. J. Holzmann, The model checker spin. Software Engineering, IEEE Transactions on, vol.23, issue.5, pp.279-295, 1997.

J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni et al., The Stanford FLASH multiprocessor, Computer Architecture, pp.302-313, 1994.

I. Melatti, R. Palmer, G. Sawaya, Y. Yang, R. M. Kirby et al., Parallel and distributed model checking in Eddy, International Journal on Software Tools for Technology Transfer, vol.3, issue.1, pp.13-25, 2009.
DOI : 10.1007/s10009-008-0094-x

S. Park and D. L. Dill, Protocol verification by aggregation of distributed transactions, CAV, pp.300-310, 1996.
DOI : 10.1007/3-540-61474-5_78

S. Schmitz and P. Schnoebolen, Algorithmic Aspects of WQO (Well-Quasy-Ordering) Theory. ESSLLI, 2012.

M. Talupur and M. R. Tuttle, Going with the Flow: Parameterized Verification Using Message Flows, 2008 Formal Methods in Computer-Aided Design, pp.1-10, 2008.
DOI : 10.1109/FMCAD.2008.ECP.14