Formal Analysis of a Hardware Dynamic Task Dispatcher with CADP

Etienne Lantreibecq 1 Wendelin Serwe 2, *
* Corresponding author
2 CONVECS - Construction of verified concurrent systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : The complexity of multiprocessor architectures for mobile multimedia applications renders their validation challenging. In addition, to provide the necessary flexibility, a part of the functionality is realized by software. Thus, a formal model has to take into account both hardware and software. In this article we report on the use of the CADP toolbox for the formal modeling and analysis of the DTD (Dynamic Task Dispatcher), a complex hardware block of an industrial hardware architecture developed by STMicroelectronics. The formal LNT model developed by an industry engineer was appropriate to discuss implementation details with the architect and enabled model-checking temporal properties expressed in MCL, which discovered a possible problem. We investigated the existence of the problem in the architect's C++ model using co-simulation of the C++ and the formal LNT models.
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https://hal.inria.fr/hal-00782069
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Submitted on : Tuesday, January 29, 2013 - 9:52:44 AM
Last modification on : Monday, October 5, 2015 - 4:58:46 PM
Document(s) archivé(s) le : Tuesday, April 30, 2013 - 3:57:03 AM

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Etienne Lantreibecq, Wendelin Serwe. Formal Analysis of a Hardware Dynamic Task Dispatcher with CADP. Science of Computer Programming, Elsevier, 2014, 80, pp.130-149. <10.1016/j.scico.2013.01.003>. <hal-00782069>

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