Polyhedral Parallel Code Generation for CUDA

Sven Verdoolaege 1 Juan Carlos Juega Albert Cohen 1 José Ignacio Gómez Christian Tenllado Francky Catthoor
1 Parkas - Parallélisme de Kahn Synchrone
DI-ENS - Département d'informatique de l'École normale supérieure, ENS Paris - École normale supérieure - Paris, Inria Paris-Rocquencourt, CNRS - Centre National de la Recherche Scientifique : UMR 8548
Abstract : This paper addresses the compilation of a sequential program for parallel execution on a modern GPU. To this end, we present a novel source-to-source compiler called PPCG. PPCG singles out for its ability to accelerate computations from any static control loop nest, generating multiple CUDA kernels when necessary. We introduce a multilevel tiling strategy and a code generation scheme for the parallelization and locality optimization of imperfectly nested loops, managing memory and exposing concurrency according to the constraints of modern GPUs. We evaluate our algorithms and tool on the entire PolyBench suite.
Type de document :
Article dans une revue
ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2013, 9 (4), <10.1145/2400682.2400713>
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https://hal.inria.fr/hal-00786677
Contributeur : Albert Cohen <>
Soumis le : dimanche 10 février 2013 - 01:40:19
Dernière modification le : mardi 13 décembre 2016 - 15:40:45

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Sven Verdoolaege, Juan Carlos Juega, Albert Cohen, José Ignacio Gómez, Christian Tenllado, et al.. Polyhedral Parallel Code Generation for CUDA. ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2013, 9 (4), <10.1145/2400682.2400713>. <hal-00786677>

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