J. Kim, H. Oh, H. Ha, S. Haeng-kang, J. Choi et al., An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems, 2012 IEEE 33rd Real-Time Systems Symposium, 2012.
DOI : 10.1109/RTSS.2012.86

T. Grandpierre and Y. Sorel, From algorithm and architecture specification to automatic generation of distributed real-time executives, Proceedings MEMOCODE, 2003.

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., The worst-case execution-time problem???overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems, vol.7, issue.3, pp.361-397, 2008.
DOI : 10.1145/1347375.1347389

K. Tindell and J. Clark, Holistic schedulability analysis for distributed hard real-time systems, Microprocessing and Microprogramming, pp.117-134, 1994.
DOI : 10.1016/0165-6074(94)90080-9

J. J. García, J. C. Gutiérrez, and M. G. Harbour, Schedulability analysis of distributed hard real-time systems with multiple-event synchronization, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000, pp.15-24, 2000.
DOI : 10.1109/EMRTS.2000.853988

M. Bertogna and M. Cirinei, Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms, 28th IEEE International Real-Time Systems Symposium (RTSS 2007), pp.149-160, 2007.
DOI : 10.1109/RTSS.2007.31

M. Kuo, R. Sinha, and P. Roop, Efficient WCRT analysis of synchronous programs using reachability, Proceedings of the 48th Design Automation Conference on, DAC '11, 2011.
DOI : 10.1145/2024724.2024837

C. Rochange, A. Bonenfant, P. Sainrat, M. Gerdes, J. Wolf et al., Wcet analysis of a parallel 3d multigrid solver executed on the merasa multicore, Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis, 2010.

F. Nemer, H. Cassé, P. Sainrat, and J. P. Bahsoun, Inter-task wcet computation for away instruction caches, IEEE Third International Symposium on Industrial Embedded Systems -SIES 2008, pp.11-13, 2008.

J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper, The Mälardalen WCET benchmarks ? past, present and future, Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis, pp.137-147, 2010.

Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury, Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores, 2009 30th IEEE Real-Time Systems Symposium, pp.1-4, 2009.
DOI : 10.1109/RTSS.2009.32

D. Hardy, T. Piquet, and I. Puaut, Using bypass to tighten wcet estimates for multicore processors with shared instruction caches, Proceedings of the 30th IEEE Real-Time Systems Symposium, RTSS 2009, pp.1-4, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00380298

J. Reineke, D. Grund, C. Berg, and R. Wilhelm, Timing predictability of cache replacement policies, Real-Time Systems, vol.28, issue.2???3, pp.99-122, 2007.
DOI : 10.1007/s11241-007-9032-3

M. Harrand and Y. Durand, Network on chip with quality of service United States patent application publication US, 2011.

L. Benini, Programming heterogeneous many-core platforms in nanometer technology : the p2012 experience Presentation in the ARTIST Summer School, 2010.

T. Grotker, System Design with SystemC, 2002.

M. Djemal, R. De-simone, F. Pêcheux, F. Wajsbürt, D. Potop-butucaru et al., Programmable routers for efficient mapping of applications onto noc-based mpsocs, Proceedings DASIP, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00787497

A. Colin and I. Puaut, A modular and retargetable framework for tree-based WCET analysis, Proceedings 13th Euromicro Conference on Real-Time Systems, pp.37-44, 2001.
DOI : 10.1109/EMRTS.2001.933995

U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, A practical automatic polyhedral parallelizer and locality optimizer, Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation, ser. PLDI '08, pp.101-113, 2008.