Communication Cost-Aware Load Balancing for Architectures with Asymetric Performance Behavior

Abstract : Current HPC platforms are highly hierarchical and present asymmetric performance behaviors. These asymmetries can be seen on the latencies of memory and network hierarchies, and processing units. In this context, an optimal task distribution for an irregular application would not only require to deal with load imbalance, but also to take into account the costs of moving data around, as the memory access and network communication costs play a major role in obtaining high efficiency. Taking both of these criteria into account is a key step to achieve performance portability on current HPC platforms. In this poster, we introduce our portable approach to improve thread/data affinity while reducing core idleness on both shared memory and distributed parallel platforms. Our approach relies on a generic view of the machine topology, with benchmarked communication costs, and information about the behavior of the parallel application. We combine this information to dynamically balance the load of the application. A load balancing algorithm named NucoLB (non-uniform communication costs load balancer) was implemented for multicore machines with non-uniform memory access design using the Charm++ Parallel System. Experimental results show that our approach leads to performance improvements of up to 20% when compared to state of the art load balancers on different parallel machines. Our future work includes extending our algorithms to different kinds of processing units, such as GPUs.
Type de document :
Communication dans un congrès
International Supercomputing Conference, ISC 2012, 2012, Hamburg, Germany, 2012
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https://hal.inria.fr/hal-00788014
Contributeur : Arnaud Legrand <>
Soumis le : mercredi 13 février 2013 - 15:03:09
Dernière modification le : jeudi 11 janvier 2018 - 06:26:53

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  • HAL Id : hal-00788014, version 1

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Laércio Pilla, Philippe Navaux, Jean-François Mehaut. Communication Cost-Aware Load Balancing for Architectures with Asymetric Performance Behavior. International Supercomputing Conference, ISC 2012, 2012, Hamburg, Germany, 2012. 〈hal-00788014〉

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