A Machine Learning-Based Approach for Thread Mapping on Transactional Memory Applications

Abstract : Thread mapping has been extensively used as a technique to efficiently exploit memory hierarchy on modern chip-multiprocessors. It places threads on cores in order to amortize memory latency and/or to reduce memory contention. However, efficient thread mapping relies upon matching application behavior with system characteristics. Particularly, Software Transactional Memory (STM) applications introduce another dimension due to its runtime system support. Existing STM systems implement several conflict detection and resolution mechanisms, which leads STM applications to behave differently for each combination of these mechanisms. In this paper we propose a machine learning-based approach to automatically infer a suitable thread mapping strategy for transactional memory applications. First, we profile several STM applications from the STAMP benchmark suite considering application, STM system and platform features to build a set of input instances. Then, such data feeds a machine learning algorithm, which produces a decision tree able to predict the most suitable thread mapping strategy for new unobserved instances. Results show that our approach improves performance up to 18.46% compared to the worst case and up to 6.37% over the Linux default thread mapping strategy.
Type de document :
Communication dans un congrès
18th Annual and International Conference on High Performance Computing (HiPC), 2011, Bangalore, India. IEEE Computer Society, pp.1-10, 2011, 〈10.1109/HiPC.2011.6152736〉
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https://hal.inria.fr/hal-00788791
Contributeur : Arnaud Legrand <>
Soumis le : vendredi 15 février 2013 - 11:16:35
Dernière modification le : mercredi 11 avril 2018 - 01:53:01

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Marcio Bastos Castro, Luıs Fabricio Wanderley Góes, Christiane Pousa Ribeiro, Murray Cole, Marcelo Cintra, et al.. A Machine Learning-Based Approach for Thread Mapping on Transactional Memory Applications. 18th Annual and International Conference on High Performance Computing (HiPC), 2011, Bangalore, India. IEEE Computer Society, pp.1-10, 2011, 〈10.1109/HiPC.2011.6152736〉. 〈hal-00788791〉

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