Memory Affinity Management for Numerical Scientific Applications over Multi-core Multiprocessors with Hierarchical Memory

Abstract : Nowadays, on Multi-core Multiprocessors with Hierarchical Memory (Non-Uniform Memory Access (NUMA) characteristics), the number of cores accessing memory banks is considerably high. Such accesses produce stress on the memory banks, generating load-balancing issues, memory contention and remote accesses. In this context, how to manage memory accesses in an efficient fashion remains an important concern. To reduce memory access costs, developers have to manage data placement on their application assuring memory affinity. The problem is: How to guarantee memory affinity for different applications/NUMA platforms and assure efficiency, portability, minimal or none source code changes (transparency) and fine control of memory access patterns? In this Thesis, our research have led to the proposal of Minas: an efficient and portable memory affinity management framework for NUMA platforms. Minas provides both explicit memory affinity management and automatic one with good performance, architecture abstraction, minimal or none application source code modifications and fine control. We have evaluated its efficiency and portability by performing some experiments with numerical scientific HPC applications on NUMA platforms. The results have been compared with other solutions to manage memory affinity.
Type de document :
Communication dans un congrès
PhD Forum of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2010, Atlanta, United States. IEEE, pp.1-4, 2010, 〈10.1109/IPDPSW.2010.5470796〉
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https://hal.inria.fr/hal-00788875
Contributeur : Arnaud Legrand <>
Soumis le : vendredi 15 février 2013 - 13:10:06
Dernière modification le : mercredi 11 avril 2018 - 01:56:25

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Christiane Pousa Ribeiro, Jean-François Mehaut, Alexandre Carissimi. Memory Affinity Management for Numerical Scientific Applications over Multi-core Multiprocessors with Hierarchical Memory. PhD Forum of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2010, Atlanta, United States. IEEE, pp.1-4, 2010, 〈10.1109/IPDPSW.2010.5470796〉. 〈hal-00788875〉

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