A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits

Smriti Joshi 1 Anne Lombardot 1 Marc Belleville 2 Edith Beigne 2 Stephane Girard 3
1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
3 MISTIS - Modelling and Inference of Complex and Structured Stochastic Systems
Inria Grenoble - Rhône-Alpes, LJK - Laboratoire Jean Kuntzmann, INPG - Institut National Polytechnique de Grenoble
Abstract : A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.
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Communication dans un congrès
DATE 2013 - Design, Automation and Test in Europe, Mar 2013, Grenoble, France. EDA Consortium, pp.1056-1057, 2013
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Contributeur : Stephane Girard <>
Soumis le : jeudi 28 mars 2013 - 08:59:56
Dernière modification le : samedi 6 février 2016 - 01:07:54
Document(s) archivé(s) le : samedi 29 juin 2013 - 04:02:23

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Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigne, Stephane Girard. A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE 2013 - Design, Automation and Test in Europe, Mar 2013, Grenoble, France. EDA Consortium, pp.1056-1057, 2013. <hal-00805478>

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