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Conference Papers Year : 2013

Precise timing analysis for direct-mapped caches

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Safety-critical systems require guarantees on their worst-case execution times. This requires modelling of speculative hardware features such as caches that are tailored to improve the average-case performance, while ignoring the worst case, which complicates the Worst Case Execution Time (WCET) analysis problem. Existing approaches that precisely compute WCET suffer from state-space explosion. In this paper, we present a novel cache analysis technique for direct-mapped instruction caches with the same precision as the most precise techniques, while improving analysis time by up to 240 times. This improvement is achieved by analysing individual control points separately, and carrying out optimisations that are not possible with existing techniques.
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Dates and versions

hal-00842368 , version 1 (11-07-2013)



Sidharta Andalam, Roopak Sinha, Partha Roop, Alain Girault, Jan Reineke. Precise timing analysis for direct-mapped caches. Design Automaton Conference, DAC, Jun 2013, Austin, TX, United States. ⟨10.1145/2463209.2488917⟩. ⟨hal-00842368⟩
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