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Reports (Research Report) Year : 2013

State-based representation of CCSL operators

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Abstract

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on verification techniques supported. The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analyses on MARTE models. This work introduces formally a state-based semantics for CCSL operators.
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Dates and versions

hal-00846684 , version 1 (19-07-2013)
hal-00846684 , version 2 (21-07-2013)
hal-00846684 , version 3 (26-07-2013)
hal-00846684 , version 4 (12-09-2013)

Identifiers

  • HAL Id : hal-00846684 , version 4

Cite

Frédéric Mallet, Jean-Vivien Millo, Yuliia Romenska. State-based representation of CCSL operators. [Research Report] RR-8334, INRIA. 2013. ⟨hal-00846684v4⟩
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