Statistical estimation of dominant physical parameters for leakage variability in 32nanometer CMOS under supply voltage variations

Abstract : The dramatic increase in leakage current has become a major issue for future IC designs. Moreover, as process variability in nano-scaled CMOS technologies induces a large spread of leakage power, leakage variability cannot be neglected anymore. In this paper, the predominant physical process parameters for static power consumption variation are analyzed for a 32 nm technology node. The presented results are confirmed by a Principal Component Analysis (PCA). A comparative analysis with 45 nm technology results is presented. In addition, a Slice Inverse Regression (SIR) method is used to study, in 32 nm, the evolution of the impact of several parameters, like the gate-length, the oxide thickness and the doping, with the supply-voltage.
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Journal of Low Power Electronics, American Scientific Publishers, 2012, 8 (1), pp.113-124. 〈10.1166/jolpe.2012.1166〉
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https://hal.inria.fr/hal-00846806
Contributeur : Brigitte Bidégaray-Fesquet <>
Soumis le : samedi 20 juillet 2013 - 16:38:19
Dernière modification le : mercredi 11 avril 2018 - 01:59:19

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Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'Agostino, Andre Juge, et al.. Statistical estimation of dominant physical parameters for leakage variability in 32nanometer CMOS under supply voltage variations. Journal of Low Power Electronics, American Scientific Publishers, 2012, 8 (1), pp.113-124. 〈10.1166/jolpe.2012.1166〉. 〈hal-00846806〉

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