Tiling With Limited Resources

Pierre-Yves Calland 1 Jack Dongarra 2 Yves Robert 1
1 REMAP - Regularity and massive parallel computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processors
Type de document :
Communication dans un congrès
L. Thiele and J. Fortes and K. Vissers and V. Taylor and T. Noll and J. Teich. Application Specific Systems, Architectures and Processors, Jul 1997, Zurich, Switzerland. IEEE Computer Society Press, pp.229-238, 1997, 〈10.1109/ASAP.1997.606829〉
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https://hal.inria.fr/hal-00856895
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Soumis le : lundi 2 septembre 2013 - 16:19:14
Dernière modification le : vendredi 20 avril 2018 - 15:44:24

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Pierre-Yves Calland, Jack Dongarra, Yves Robert. Tiling With Limited Resources. L. Thiele and J. Fortes and K. Vissers and V. Taylor and T. Noll and J. Teich. Application Specific Systems, Architectures and Processors, Jul 1997, Zurich, Switzerland. IEEE Computer Society Press, pp.229-238, 1997, 〈10.1109/ASAP.1997.606829〉. 〈hal-00856895〉

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