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Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Abderahman Kriouile 1, * Wendelin Serwe 1
* Corresponding author
1 CONVECS - Construction of verified concurrent systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : System-on-Chip (SoC) architectures integrate now many different components, such as processors, accelerators, memory, and I/O blocks, some but not all of which may have caches. Because the validation effort with simulation-based validation techniques, as currently used in industry, grows exponentially with the complexity of the SoC, we investigate in this paper the use of formal verification techniques. More precisely, we use the CADP toolbox to develop and validate a generic formal model of an SoC compliant with the recent ACE specification proposed by ARM to implement system-level coherency.
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Contributor : Wendelin Serwe <>
Submitted on : Tuesday, September 10, 2013 - 12:25:20 PM
Last modification on : Tuesday, February 9, 2021 - 3:10:03 PM
Long-term archiving on: : Thursday, December 12, 2013 - 10:07:17 AM


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  • HAL Id : hal-00858521, version 1


Abderahman Kriouile, Wendelin Serwe. Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip. FMICS - 18th International Workshop on Formal Methods for Industrial Critical Systems, ERCIM Working Group on Formal Methods for Industrial Critical Systems (FMICS), Sep 2013, Madrid, Spain. pp.108-122. ⟨hal-00858521⟩



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