S. Agarwala, A. Rajagopal, A. Hill, M. Joshi, S. Mullinnix et al., Peter Groves, and Others. A 65nm C64x+ multi-core DSP platform for communications infrastructure, Solid-State Circuits Conference, pp.262-601, 2007.

J. Auerbach, D. F. Bacon, I. Burcea, P. Cheng, and S. J. Fink, Rodric Rabbah, and Sunil Shukla. A compiler and runtime for heterogeneous computing, pp.271-276, 2012.

J. Auerbach, D. F. Bacon, I. Burcea, P. Cheng, and S. J. Fink, Rodric Rabbah, and Sunil Shukla. A compiler and runtime for heterogeneous computing, pp.271-276, 2012.

K. Van-berkel, F. Heinle, P. P. Meuwissen, K. Moerman, and M. Weiss, Vector Processing as an Enabler for Software-Defined Radio in Handheld Devices, EURASIP Journal on Advances in Signal Processing, vol.2005, issue.16, pp.2613-2625, 2005.
DOI : 10.1155/ASP.2005.2613

G. Bilsen, M. Engels, R. Lauwreins, and J. Peperstraete, Cycle-static dataflow, IEEE Transactions on Signal Processing, vol.44, issue.2, pp.397-408, 1996.
DOI : 10.1109/78.485935

D. Black-schaffer, Block parallel programming for real-time applications on multi-core processors, 2008.

B. Bougard, B. D. Sutter, and D. Verkest, A coarse-grained array accelerator for software-defined radio, IEEE Micro, pp.41-50, 2008.

P. Boulet, Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00128840

I. Buck, T. Foley, D. Reiter-horn, J. Sugerman, K. Fatahalian et al., Brook for GPUs, ACM Transactions on Graphics, vol.23, issue.3, pp.777-786, 2004.
DOI : 10.1145/1015706.1015800

J. Castrillon, R. Leupers, and G. Ascheid, MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs, IEEE Transactions on Industrial Informatics, vol.9, issue.1, pp.1-19, 2011.
DOI : 10.1109/TII.2011.2173941

J. Castrillon, S. Schürmans, A. Stulova, W. Sheng, T. Kempf et al., Component-based waveform development: the Nucleus tool flow for efficient and portable software defined radio, Analog Integrated Circuits and Signal Processing, vol.93, issue.2, pp.173-190, 2011.
DOI : 10.1007/s10470-011-9670-1

R. Chandra, L. Dagum, D. Kohr, D. Maydan, J. Mcdonald et al., Parallel programming in OpenMP, 2001.

F. Clermidy, R. Lemaire, X. Popon, D. Ktenas, and Y. Thonnart, An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, pp.449-456, 2009.
DOI : 10.1109/DSD.2009.200

A. Cohen and E. Rohou, Processor virtualization and split compilation for heterogeneous multicore embedded systems, Proceedings of the 47th Design Automation Conference on, DAC '10, p.102, 2010.
DOI : 10.1145/1837274.1837303

URL : https://hal.archives-ouvertes.fr/inria-00472274

P. De, O. Castro, S. Louise, and D. Barthou, A multidimensional array slicing dsl for stream programming, Proceedings of the 2010 International Conference on Complex, Intelligent and Software Intensive Systems, CISIS '10, pp.913-918, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00551572

J. Delahaye, J. Palicot, C. Moy, and P. Leray, Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform, 2007 16th IST Mobile and Wireless Communications Summit, pp.16-17, 2007.
DOI : 10.1109/ISTMWC.2007.4299250

URL : https://hal.archives-ouvertes.fr/hal-00147698

V. Derudder, . Bougard, . Couvreur, . Dewilde, . Dupont et al., 14 nJ/b digital baseband multi processor system-on-chip for SDRs, VLSI Circuits, Symposium on, pp.292-293, 2009.

J. Eker, J. W. Janneck, E. A. Lee, J. Liu, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, pp.127-144, 2003.
DOI : 10.1109/JPROC.2002.805829

K. Fatahalian, D. Reiter-horn, T. J. Knight, L. Leem, M. Houston et al., Sequoia: Programming the Memory Hierarchy, ACM/IEEE SC 2006 Conference (SC'06), 2006.
DOI : 10.1109/SC.2006.55

P. Fradet, A. Girault, and P. Poplavko, SPDF: A schedulable parametric data-flow MoC, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.769-774, 2012.
DOI : 10.1109/DATE.2012.6176572

URL : https://hal.archives-ouvertes.fr/hal-00744376

J. Glossner, D. Iancu, M. Moudgill, G. Nacer, S. Jinturkar et al., The Sandbridge SB3011 Platform, EURASIP Journal on Embedded Systems, pp.1-16, 2007.

R. Carlos, C. B. Aguayo-gonzález, S. Dietrich, H. I. Sayed, J. D. Volos et al., Open-source sca-based core framework and rapid development tools enable software-defined radio education and research, Comm. Mag, vol.47, pp.48-55, 2009.

J. Gonzalez-pina, R. Ameur-boulifa, and R. Pacalet, Diplodocusdf, a domainspecific modelling language for software defined radio applications A portable video tool library for mpeg reconfigurable video coding using llvm representation, 38th Euromicro Conference on Software Engineering and Advanced Applications Wipliez, F. Prêteux, and Mickaël Raulet Design and Architectures for Signal and Image Processing 2010 Conference on, pp.1-8, 2010.

T. Goubier, R. Sirdey, S. Louise, and V. David, ?C: A programming model and language for embedded manycores. Algorithms and Architectures for parallel processing, pp.385-394, 2011.

J. Gummaraju, J. Coburn, Y. Turner, and M. Rosemblum, Streamware: programming general-purpose multicore processors using streams, pp.297-307, 2008.

P. Horrein, C. Hennebert, and F. Pétrot, Adapting a SDR environment to GPU architectures, Wireless Innovation Forum (SDR Forum), 2011.

P. Horrein, C. Hennebert, and F. Pétrot, Integration of GPU Computing in a Software Radio Environment, Journal of Signal Processing Systems, vol.64, issue.3, pp.55-65, 2011.
DOI : 10.1007/s11265-011-0639-1

URL : https://hal.archives-ouvertes.fr/hal-01332719

C. Hsu, J. L. Pino, and F. Hu, A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer, Proceedings of the 47th Design Automation Conference on, DAC '10, pp.18-23, 2010.
DOI : 10.1145/1837274.1837282

P. Jääskeläinen, C. S. De-la-lama, P. Huerta, and J. Takala, OpenCL-based design methodology for application-specific processors, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp.223-230, 2010.
DOI : 10.1109/ICSAMOS.2010.5642061

C. Jalier, D. Lattard, G. Jerraya, P. Sassatelli, L. Benoit et al., Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.184-189, 2010.
DOI : 10.1109/DATE.2010.5457213

URL : https://hal.archives-ouvertes.fr/lirmm-00436680

W. M. Johnston, R. J. Hanna, and . Millar, Advances in dataflow programming languages, ACM Computing Surveys, vol.36, issue.1, pp.1-34, 2004.
DOI : 10.1145/1013208.1013209

G. Kahn, The semantics of a simple language for parallel programming, Information processing, pp.471-475, 1974.

F. Labonte, P. Mattson, W. Thies, I. Buck, C. Kozyrakis et al., The stream virtual machine, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004., pp.267-277, 2004.
DOI : 10.1109/PACT.2004.1342560

O. Lazrak, P. Leray, and C. Moy, HDCRAM Proof-of-Concept for Opportunistic Spectrum Access, 2012 15th Euromicro Conference on Digital System Design, 2012.
DOI : 10.1109/DSD.2012.70

URL : https://hal.archives-ouvertes.fr/hal-00737401

T. Limberg, M. Winter, M. Bimberg, R. Klemm, E. Matus et al., A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals, ESSCIRC 2008, 34th European Solid-State Circuits Conference, pp.466-469, 2008.
DOI : 10.1109/ESSCIRC.2008.4681893

Y. Lin, R. Mullenix, M. Woh, S. Mahlke, T. Mudge et al., SPEX: A programming language for software defined radio, pp.13-17, 2006.

M. D. Linderman, J. D. Collins, H. Wang, and T. H. Meng, Merge : A Programming Model for Heterogeneous Multi-core Systems, pp.287-296, 2008.

A. Lodi, A. Cappelli, M. Bocchi, C. Mucci, M. Innocenti et al., XiSystem: a XiRisc-based SoC with reconfigurable IO module. Solid-State Circuits, IEEE Journal, issue.1, pp.4185-96, 2006.

J. Martin, C. Bernard, F. Clermidy, and Y. Durand, A Microprogrammable Memory Controller for high-performance dataflow applications, 2009 Proceedings of ESSCIRC, pp.348-351, 2009.
DOI : 10.1109/ESSCIRC.2009.5325981

B. Mei, S. Vernalde, D. Verkest, H. De-man, and R. Lauwereins, DRESC: A retargetable compiler for coarse-grained reconfigurable architectures, IEEE International Conference on, pp.166-173, 2002.

. Minden, KUAR: A Flexible Software-Defined Radio Development Platform, 2007 2nd IEEE International Symposium on New Frontiers in Dynamic Spectrum Access Networks, pp.428-439, 2007.
DOI : 10.1109/DYSPAN.2007.62

J. Mitola, Software Radios Survey, Critical Evaluation and Future Directions, Telesystems Conference, pp.13-15, 1992.
DOI : 10.1109/ntc.1992.267870

D. Nussbaum, K. Kalfallah, C. Moy, A. Nafkha, P. Lerary et al., Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, pp.435-440, 2009.
DOI : 10.1109/DSD.2009.123

URL : https://hal.archives-ouvertes.fr/hal-00401414

M. Palkovic, P. Raghavan, M. Li, A. Dejonghe, and L. , Future Software-Defined Radio Platforms and Mapping Flows, IEEE Signal Processing Magazine, vol.27, issue.2, pp.22-33, 2010.
DOI : 10.1109/MSP.2009.935386

M. Palkovic, P. Raghavan, M. Li, A. Dejonghe, and L. , Future Software-Defined Radio Platforms and Mapping Flows, IEEE Signal Processing Magazine, vol.27, issue.2, pp.22-33, 2010.
DOI : 10.1109/MSP.2009.935386

D. Pulley and R. Baines, Software defined baseband processing for 3G base stations, Fourth International Conference on 3G Mobile Communication Technologies, pp.123-127, 2003.
DOI : 10.1049/cp:20030350

U. Ramacher, Software-Defined Radio Prospects for Multistandard Mobile Phones, Computer, vol.40, issue.10, pp.62-69, 2007.
DOI : 10.1109/MC.2007.362

U. Ramacher, Architecture and implementation of a Software-Defined Radio baseband processor, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.2193-2196, 2011.
DOI : 10.1109/ISCAS.2011.5938035

V. S. Saito and V. I. Sugiyama, Single-Chip Baseband Signal Processor for Software- Defined Radio, FUJITSU Sci. Tech. J, vol.42, issue.2, pp.240-247, 2006.

C. Schmidt-knorreck, R. Pacalet, A. Minwegen, U. Deidersen, T. Kempf et al., Flexible Front-End Processing for Software Defined Radio Applications using Application Specific Instruction-Set Processors, DASIP 2012, Conference on Design and Architectures for Signal and Image Processing, pp.23-25, 2012.

M. J. Schulte, J. Glossner, and S. Mamidi, Mayan Moudgill, and S. Vassiliadis. A low-power multithreaded processor for baseband communication systems, Computer Systems: Architectures, Modeling, and Simulation, pp.333-346, 2004.

F. Siyoum, M. Geilen, O. Moreira, R. Nas, and H. Corporaal, Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications, 2011 International Symposium on System on Chip (SoC), pp.14-21, 2011.
DOI : 10.1109/ISSOC.2011.6089222

P. D. Sutton, J. Lotze, H. Lahlou, S. A. Fahmy, K. E. Nolan et al., Iris: an architecture for cognitive radio networking testbeds, IEEE Communications Magazine, vol.48, issue.9, pp.114-122, 2010.
DOI : 10.1109/MCOM.2010.5560595

K. Tan, H. Liu, J. Zhang, Y. Zhang, J. Fang et al., Sora, Communications of the ACM, vol.54, issue.1, pp.99-107, 2011.
DOI : 10.1145/1866739.1866760

W. Thies, Language and compiler support for stream programs, 2009.

D. N. Truong, W. H. Cheng, T. Mohsenin, Z. Yu, A. T. Jacobson et al., A 167-processor computational platform in 65 nm CMOS. Solid-State Circuits, IEEE Journal, vol.44, issue.4, pp.123-127, 2009.

T. Ulversoy, Software Defined Radio: Challenges and Opportunities, IEEE Communications Surveys & Tutorials, vol.12, issue.4, pp.531-550, 2010.
DOI : 10.1109/SURV.2010.032910.00019

P. H. Wang, J. D. Collins, G. N. Chinya, H. Jiang, X. Tian et al., Exochi: architecture and programming environment for a heterogeneous multi-core multithreaded system, Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation, PLDI '07, pp.156-166, 2007.

M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti et al., SODA: A Low-power Architecture For Software Radio, 33rd International Symposium on Computer Architecture (ISCA), pp.89-101, 2006.

M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge et al., Mladen Wilder, and Others. From SODA to scotch: The evolution of a wireless baseband processor, Microarchitecture, MICRO. 41st IEEE/ACM International Symposium on, pp.152-163, 2008.

Q. Zhang, .. B. Kokkeler, G. J. Smit, and K. H. Walters, Cognitive Radio baseband processing on a reconfigurable platform, Inria RESEARCH CENTRE GRENOBLE ? RHÔNE-ALPES Inovallée 655 avenue de l'Europe Montbonnot 38334 Saint Ismier Cedex Publisher Inria Domaine de Voluceau -Rocquencourt BP 105 -78153 Le Chesnay Cedex inria.fr ISSN, pp.33-46, 2009.
DOI : 10.1016/j.phycom.2009.02.008