Boundness Issues in CCSL Specifications - Inria - Institut national de recherche en sciences et technologies du numérique Accéder directement au contenu
Communication Dans Un Congrès Année : 2013

Boundness Issues in CCSL Specifications

Résumé

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on verification techniques supported. The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analyses on MARTE models. This work introduces formally a state-based semantics for CCSL operators and then focuses on the analysis capabilities of MARTE/CCSL and more particularly on boundness issues. The approach is illustrated on one simple example where the architecture plays an important role. We describe a process where the logical description of the application is progressively refined to take into account the candidate execution platforms through allocation.

Dates et versions

hal-00877598 , version 1 (28-10-2013)

Identifiants

Citer

Frédéric Mallet, Jean-Vivien Millo. Boundness Issues in CCSL Specifications. ICFEM 2013 - 15th International Conference on Formal Engineering Methods, Oct 2013, Queenstown, New Zealand. pp.20-35, ⟨10.1007/978-3-642-41202-8_3⟩. ⟨hal-00877598⟩
157 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More