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Master-Slave Control structure for massively parallel System on Chip

Hana Krichene 1, 2 Mouna Baklouti 1 Jean-Luc Dekeyser 2 Philippe Marquet 2 Mohamed Abid 1
2 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages
Université de Lille, Sciences et Technologies, Inria Lille - Nord Europe, CNRS - Centre National de la Recherche Scientifique
Abstract : The performance of massively parallel processing system depends mostly on the control configuration that is inherently part of the system. In particular, centralized control configuration is rigid and limits system scalability, and distributed control configuration is difficult to control in processing elements (PEs) interaction. Maintaining a flexible autonomous computation coupled with regular synchronous communication can assure a efficient parallel processing. The master-slave control structure is specified in such a way that previous features of the massively parallel System-on-Chip (mpSoC) are preserved and performance is improved. In this paper, we define the prototyping of a master-slave control structure for mpSoC in a FPGA-based platform. The structure implementation and related experiments using the vhdl language running on virtex6 ml605 of Xilinx board are described.
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https://hal.inria.fr/hal-00906906
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Submitted on : Wednesday, November 20, 2013 - 2:29:52 PM
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Hana Krichene, Mouna Baklouti, Jean-Luc Dekeyser, Philippe Marquet, Mohamed Abid. Master-Slave Control structure for massively parallel System on Chip. DSD SEAA - 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. ⟨hal-00906906⟩

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