Safe CCSL Specifications and Marked Graphs

Frédéric Mallet 1, * Jean-Vivien Millo 1 Robert de Simone 1
* Corresponding author
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : The Clock Constraint Specification Language (CCSL) proposes a rich polychronous time model dedicated to the specification of constraints on logical clocks: i.e., sequences of event occurrences. A priori independent clocks are progressively constrained through a set of clock operators that define when an event may occur or not. These operators can be described as labeled transition systems that can potentially have an infinite number of states. A CCSL specification can be scheduled by performing the synchronized product of the transition systems for each operator. Even when some of the composed transition systems are infinite, the number of reachable states in the product may still be finite: the specification is safe. The purpose of this paper is to propose a sufficient condition to detect that the product is actually safe. This is done by abstracting each CCSL constraint (relation and expression) as a marked graph. Detecting that some specific places, called counters, in the resulting marked graph are safe is sufficient to guarantee that the composition is safe.
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Frédéric Mallet, Jean-Vivien Millo, Robert de Simone. Safe CCSL Specifications and Marked Graphs. MEMOCODE - 11th IEEE/ACM International Conference on Formal Methods and Models for Codesign, Oct 2013, Portland, United States. pp.157-166. ⟨hal-00913962⟩

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