Skip to Main content Skip to Navigation
Conference papers

Buffer Minimization in Earliest-Deadline First Scheduling of Dataflow Graphs

Adnan Bouakaz 1, * Jean-Pierre Talpin 1
* Corresponding author
1 ESPRESSO - Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : Symbolic schedulability analysis of dataflow graphs is the process of synthesizing the timing parameters (i.e. periods, phases, and deadlines) of actors so that the task system is schedulable and achieves a high throughput when using a specific scheduling policy. Furthermore, the resulted schedule must ensure that communication buffers are underflow- and overflow-free. This paper describes a (partitioned) earliest -deadline first symbolic schedulability analysis of dataflow graphs that minimizes the buffering requirements. Our scheduling analysis consists of three major steps. (1) The construction of an abstract affine schedule of the graph that excludes overflow and underflow exceptions and minimizes the buffering requirements assuming some precedences between jobs. (2) Symbolic deadlines adjustment that guarantees precedences without the need for lock-based synchronizations. (3) The concretization of the affine schedule using a symbolic, fast-converging, processor-demand analysis for both uniprocessor and multiprocessor systems. Experimental results show that our technique improves the buffering requirements in many cases.
Document type :
Conference papers
Complete list of metadata

https://hal.inria.fr/hal-00916485
Contributor : Adnan Bouakaz <>
Submitted on : Tuesday, December 10, 2013 - 12:41:55 PM
Last modification on : Tuesday, June 15, 2021 - 4:26:55 PM

Links full text

Identifiers

Citation

Adnan Bouakaz, Jean-Pierre Talpin. Buffer Minimization in Earliest-Deadline First Scheduling of Dataflow Graphs. ACM SIG- PLAN/SIGBED conference on languages, compilers and tools for embedded systems, Jun 2013, Seattle, WA, United States. pp.133-142, ⟨10.1145/2499369.2465558⟩. ⟨hal-00916485⟩

Share

Metrics

Record views

334