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Runtime dependency analysis for loop pipelining in High-Level Synthesis

Mythri Alle 1 Antoine Morvan 1 Steven Derrien 1 
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Research on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient implementations. In this work, we propose to address this issue by leveraging well-known techniques used in superscalar processors to perform runtime memory disambiguation. Our approach, implemented as a source-to-source transformation at the C level, demonstrates significant performance improvements for a moderate increase in area while retaining portability among HLS tools.
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Contributor : François Charot Connect in order to contact the contributor
Submitted on : Friday, December 20, 2013 - 1:18:45 PM
Last modification on : Tuesday, June 7, 2022 - 4:56:02 PM


  • HAL Id : hal-00921416, version 1


Mythri Alle, Antoine Morvan, Steven Derrien. Runtime dependency analysis for loop pipelining in High-Level Synthesis. 50th Design Automation Conference (DAC),, May 2013, Austin, United States. ⟨hal-00921416⟩



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