Runtime dependency analysis for loop pipelining in High-Level Synthesis

Abstract : Research on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient implementations. In this work, we propose to address this issue by leveraging well-known techniques used in superscalar processors to perform runtime memory disambiguation. Our approach, implemented as a source-to-source transformation at the C level, demonstrates significant performance improvements for a moderate increase in area while retaining portability among HLS tools.
Type de document :
Communication dans un congrès
50th Design Automation Conference (DAC),, May 2013, Austin, United States. ACM, 2013
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https://hal.inria.fr/hal-00921416
Contributeur : François Charot <>
Soumis le : vendredi 20 décembre 2013 - 13:18:45
Dernière modification le : mercredi 11 avril 2018 - 02:00:36

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  • HAL Id : hal-00921416, version 1

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Mythri Alle, Antoine Morvan, Steven Derrien. Runtime dependency analysis for loop pipelining in High-Level Synthesis. 50th Design Automation Conference (DAC),, May 2013, Austin, United States. ACM, 2013. 〈hal-00921416〉

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