Real-time computing systems are increasingly used in several industrial domains such as aerospace, avionic, rail, and automotive. During the manufacturing process, designers need development tools for the verification and the validation (V&V) of modern and complex systems. Today, the simulation phase is considered as an unavoidable part of the V&V cycle. In order to meet the application requirements in terms of increasing computation rate and real-time, dedicated simulators should be used. In the face of these challenges, hardware designers are directed towards reconfigurable computing with the usage of heterogeneous CPU/FPGA systems. However, there is a lack of real-time simulation environments able to deal with the execution of applications on such heterogeneous systems. This research investigates the problem of soft real-time simulation environment supporting CPU/FPGA hardware architecture. Our environment runs a simulation project as a cyclic graph of synchronized models. This project is monitored with a supervisor that integrates a heuristic allowing an efficient dynamic mapping on the hardware architecture in order to avoid real-time constraint violation. The monitoring kernel module ensures the calculation of cores' load. These values help the supervisor to take the decision of reconfiguration at runtime. The efficiency of our simulation environment is validated through an avionic case-study that imposes real-time constraints in the order of milliseconds.