An FPGA Configuration Stream Architecture Supporting Seamless Hardware Accelerator Migration

Abstract : Most of the available commercial Field Programmable Gate Arrays (FPGA) use an addressable memory organized around an array of N-bit words of Static RAM (SRAM) cells. Such configuration memory is traditionally programmed by writing, to each word, the corresponding bit-stream data at runtime. In the growing domain of Dynamic Partial Reconfiguration, this leads to long reconfiguration time of dynamic regions. We propose a novel approach to task relocation in an FPGA-based reconfigurable fabric, allowing for offline design, routing and unfinalized placement of hardware IPs and dynamic placement of the corresponding bit-streams at runtime.
Type de document :
Communication dans un congrès
ConfigComp'2013, Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology, Architectures and Design Tools, held in conjunction to the DATE 2013 conference, Mar 2013, Grenoble, France. 2013
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https://hal.inria.fr/hal-00931572
Contributeur : Olivier Sentieys <>
Soumis le : mercredi 15 janvier 2014 - 14:43:48
Dernière modification le : mardi 16 janvier 2018 - 15:54:13

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  • HAL Id : hal-00931572, version 1

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Christophe Huriaux, Olivier Sentieys, Antoine Courtay. An FPGA Configuration Stream Architecture Supporting Seamless Hardware Accelerator Migration. ConfigComp'2013, Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology, Architectures and Design Tools, held in conjunction to the DATE 2013 conference, Mar 2013, Grenoble, France. 2013. 〈hal-00931572〉

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