Hardware Description Language Design of Sigma-Delta Fractional-N Phase-Locked Loop for Wireless Applications

Abstract : This paper discusses a systematic design of a Sigma-Delta fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
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World Academy of Science, Engineering and Technology, WASET, 2009, 28, pp.1035-1042
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https://hal.inria.fr/hal-00947400
Contributeur : Ahmed El Oualkadi <>
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Dernière modification le : lundi 24 septembre 2018 - 18:02:14
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  • HAL Id : hal-00947400, version 1

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Ahmed El Oualkadi, Abdellah Ait Ouahman. Hardware Description Language Design of Sigma-Delta Fractional-N Phase-Locked Loop for Wireless Applications. World Academy of Science, Engineering and Technology, WASET, 2009, 28, pp.1035-1042. 〈hal-00947400〉

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