J. P. Queille and J. Sifakis, Specification and verification of concurrent systems in CESAR, Proceedings of the International Symposium in Programming, 1982.
DOI : 10.1007/3-540-11494-7_22

E. M. Clarke, E. A. Emerson, and A. P. Sistla, Automatic Verification of finite state concurrent systems using temporal logic specifications, ACM TOPLA, 1986.

M. O. Rabin, Probabilistic algorithms, Algorithms and Complexity: New Directions and Recent Results, pp.2-39, 1976.

R. Motwani and P. Raghavan, Randomized Algorithms, 2005.

J. Burch, E. Clarke, D. Dill, L. Hwang, and K. Mcmillan, Symbolic model checking: 10/sup 20/ states and beyond, [1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science, pp.428-439, 1990.
DOI : 10.1109/LICS.1990.113767

R. Pelánek, T. Han?l, I. Cerná, and L. Brim, Enhancing random walk state space exploration, Proceedings of the 10th international workshop on Formal methods for industrial critical systems , FMICS '05, pp.98-105, 2005.
DOI : 10.1145/1081180.1081193

C. H. West, Protocol validation by random state exploration, International Symposium on Protocol Specification, testing and Verification, 1986.

D. Owen, T. Menzies, and . Lurch, A lightweight alternative to model checking, Proc. of Software Engineering and Knowledge Engineering (SEKE'2003), pp.158-165

R. Grosu and S. A. Smolka, Monte Carlo Model Checking, Proc. of Tools and Algorithms for Construction and Analysis of Systems (TACAS 2005), pp.271-286, 2005.
DOI : 10.1007/978-3-540-31980-1_18

R. Grosu, X. Huang, S. A. Smolka, W. Tan, and S. Tripakis, Deep Random Search for Efficient Model Checking of Timed Automata, Proc. of MW'06, the 7th Monterey Workshop on Composition of Embedded Systems, pp.37-48, 2006.
DOI : 10.1007/978-3-540-77419-8_7

P. Haslum, Model checking by random walk, Proc. of ECSEL Workshop, 1999.

M. Mihail and C. H. Papadimitriou, On the random walk method for protocol testing, Proc. Computer-Aided Verification, pp.132-141, 1994.
DOI : 10.1007/3-540-58179-0_49

H. Sivaraj and G. Golpalakrishnan, Random Walk Based Heuristic Algorithms for Distributed Memory Model Checking, Proc. of Parallel and Distributed Model Checking (PDMC'03), 2003.
DOI : 10.1016/S1571-0661(05)80096-9

A. Kuehlmann, K. L. Mcmillan, and R. K. Brayton, Probabilistic state space search, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), pp.574-579, 1999.
DOI : 10.1109/ICCAD.1999.810713

J. Geldenhyus, State Caching Reconsidered, LNCS, vol.2989, pp.23-39, 2004.
DOI : 10.1007/978-3-540-24732-6_3

P. Godefroid, G. J. Holzmann, and D. Pirottin, State space caching revisited, Proc. of Computer Aided Verification, pp.178-191, 1992.
DOI : 10.1007/3-540-56496-9_15

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

P. Godefroid, Using partial orders to improve automatic verification methods, Proc. 2nd International Conference on Computer Aided Verification, pp.176-185, 1990.
DOI : 10.1007/BFb0023731

P. Godefroid, On the costs and benefits of using partial order methods for the verification of concurrent systems, Proc. Workshop on Partial Order Methods in Verification, DIMACS series, pp.289-303, 1996.

E. Tronci, G. D. Penna, B. Intrigila, and M. Venturini, A probabilistic approach to automatic verification of concurrent systems, Proceedings Eighth Asia-Pacific Software Engineering Conference, 2001.
DOI : 10.1109/APSEC.2001.991495

F. Lin, P. Chu, and M. Liu, Protocol verification using reachability analysis: the state space explosion problem and relief strategies, ACM SIGCOMM Computer Communication Review, vol.17, issue.5, pp.126-134, 1987.
DOI : 10.1145/55483.55496

G. J. Holzmann, An analysis of bi-state hashing, Proc. of Protocol Specification, Testing and Verification, pp.301-314, 1995.

G. J. Holzmann, Automated Protocol Validation in Argos: Assertion Proving and Scatter Searching, IEEE trans. on Software engineering, pp.683-696126, 1987.
DOI : 10.1109/TSE.1987.233206

U. Feige, A tight upper bound on the cover time for random walks on graphs, Random Structures & Algorithms, vol.4, issue.1, pp.51-54, 1995.
DOI : 10.1002/rsa.3240060106

U. Stem and D. L. Dill, Improved probabilistic verification by hash compaction, Advanced Research Working Conference on Correct Hardware Design and Verification Methods, pp.206-224, 1995.

R. Nalumasu and G. Gopalakrishnan, An efficient partial order reduction algorithm with an alternative provision implementation, Formal Methods for System Design, pp.206-224, 1995.

E. M. Clarke, R. Enders, T. Filkorn, and S. Jha, Exploiting symmetry in temporal logic model checking, Formal Methods in System Design, vol.8, issue.Nos. 4/5, pp.77-104, 1996.
DOI : 10.1007/BF00625969

M. Bozga, J. C. Fernandez, L. Ghirvu, S. Graf, J. P. Krimm et al., IF: A Validation Environment for Timed Asynchronous Systems, Proc. Computer- Aided Verification volume 1855 of LNCS, pp.543-547, 2000.
DOI : 10.1007/10722167_41

URL : https://hal.archives-ouvertes.fr/hal-00369415