K. Chapman, Fast integer multipliers fit in FPGAs (EDN 1993 design idea winner), " EDN magazine, p.80, 1993.

M. Wirthlin, Constant Coefficient Multiplication Using Look-Up Tables, The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol.36, issue.1, pp.7-15, 2004.
DOI : 10.1023/B:VLSI.0000008066.95259.b8

F. De-dinechin, H. Takeugming, and J. Tanguy, A 128-tap complex FIR filter Processing 20 giga-samples/s in a single FPGA, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers, 2010.
DOI : 10.1109/ACSSC.2010.5757684

URL : https://hal.archives-ouvertes.fr/ensl-00542950

N. Brunie, F. De-dinechin, M. Istoan, G. Sergent, K. Illyes et al., Arithmetic core generation using bit heaps, 2013 23rd International Conference on Field programmable Logic and Applications, 2013.
DOI : 10.1109/FPL.2013.6645544

URL : https://hal.archives-ouvertes.fr/ensl-00738412

H. Parendeh-afshar, A. Neogy, P. Brisk, and P. Ienne, Compressor tree synthesis on commercial high-performance FPGAs, ACM Transactions on Reconfigurable Technology and Systems, vol.4, issue.4, 2011.
DOI : 10.1145/2068716.2068725

R. Kumar, A. Mandal, and S. P. Khatri, An efficient arithmetic sum-ofproduct (SOP) based multiplication approach for FIR filters and DFT, International Conference on Computer Design (ICCD, pp.195-200, 2012.

F. De-dinechin and B. Pasca, Designing Custom Arithmetic Data Paths with FloPoCo, IEEE Design & Test of Computers, vol.28, issue.4, pp.18-27, 2011.
DOI : 10.1109/MDT.2011.44

URL : https://hal.archives-ouvertes.fr/ensl-00646282

L. D. Srivastava and A. Chandrakasan, Some schemes for parallel multipliers Alta Frequenza Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching, ACM IEEE Design Automation Conference, pp.349-356, 1965.

N. Boullis and A. Tisserand, Some Optimizations of Hardware Multiplication by Constant Matrices, IEEE Transactions on Computers, vol.54, issue.10, pp.1271-1282, 2005.
DOI : 10.1109/TC.2005.168

URL : https://hal.archives-ouvertes.fr/lirmm-00113092

M. Mehendale, S. D. Sherlekar, and G. Venkatesh, Synthesis of multiplier-less FIR filters with minimum number of additions, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), pp.668-671, 1995.
DOI : 10.1109/ICCAD.1995.480201

Y. Voronenko and M. Püschel, Multiplierless multiple constant multiplication, ACM Transactions on Algorithms, vol.3, issue.2, 2007.
DOI : 10.1145/1240233.1240234

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

L. Aksoy, E. Costa, P. Flores, and J. Monteiro, Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.6, pp.1013-1026, 2008.
DOI : 10.1109/TCAD.2008.923242

S. White, Applications of distributed arithmetic to digital signal processing: a tutorial review, IEEE ASSP Magazine, vol.6, issue.3, pp.4-19, 1989.
DOI : 10.1109/53.29648

M. Kumm, K. Möller, and P. Zipf, Dynamically reconfigurable FIR filter architectures with fast reconfiguration, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013.
DOI : 10.1109/ReCoSoC.2013.6581517