A. Benaini and Y. Robert, Space-minimal systolic arrays for Gaussian elimination and the algebraic path problem, Parallel Computing, pp.15-211, 1990.

J. C. Bermond, C. Peyrat, I. Sakho, and M. Tchuente, Parallelisation of the Gaussian elimination on systolic arrays, Journal of Parallel and Distributed Computing, pp.33-69, 1996.

J. C. Bermond, C. Peyrat, I. Sakho, and M. Tchuente, Parallelisation of the Gauss elimination on systolic arrays, Internal Report, LRI, p.430, 1988.

J. Bu and E. F. Deprettere, Processor clustering for the design of optimal fixed-size systolic arrays, Proc. Sixth Int'l Parallel Processing Symp, pp.275-282, 1992.

P. Clauss, Optimal mapping of systolic algorithms by regular instruction shifts, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94), pp.224-235, 1990.
DOI : 10.1109/ASAP.1994.331801

P. Clauss, C. Mongenet, and G. R. Perrin, Calculus of space-optimal mappings of systolic algorithms on processor arrays, IEEE Int. Conf. on Application Specific Array Processors, pp.591-602, 1990.

A. Darte, T. Risset, and Y. Robert, Synthesizing systolic arrays: Some recent developments. Int. Conf. on Application Specific Array Processors, pp.372-386, 1991.

P. Fautrier, Dataflow analysis of array and scalar references, International Journal of Parallel Programming, vol.24, issue.4, pp.23-53, 1991.
DOI : 10.1007/BF01407931

K. N. Ganapathy and B. W. Wah, Optimal synthesis of algorithm-specific lower-dimensional processor arrays, IEEE Transactions on Parallel and Distributed Systems, vol.7, issue.3, pp.274-287, 1996.
DOI : 10.1109/71.491581

M. Griebl and C. Lengauer, The loop parallilizer LooPo, Proc. Sixth Workshop On Compilers For Parallel Computers, M. Gerndt Konferenzen des Forschungszentrums Jülich, pp.311-320, 1996.

A. Gupta, F. G. Gustavson, M. Joshi, and S. Toledo, The design, implementation, and evaluation of a banded linear solver for distributed-memory parallel computers, IBM Research Report, vol.19, issue.6, p.20481, 1996.
DOI : 10.1007/3-540-62095-8_35

R. M. Karp, R. E. Miller, and S. Winograd, The Organization of Computations for Uniform Recurrence Equations, Journal of the ACM, vol.14, issue.3, pp.563-590, 1967.
DOI : 10.1145/321406.321418

H. T. Kung, Why systolic architectures?, Computer, vol.15, issue.1, pp.37-46, 1980.
DOI : 10.1109/MC.1982.1653825
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.643.6701

L. Lamport, The parallel execution of DO loops, Communications of the ACM, vol.17, issue.2, pp.83-93, 1974.
DOI : 10.1145/360827.360844

B. Louka and M. Tchuenté, Dynamic programming on two-dimensional systolic arrays, Information Processing Letters, vol.29, issue.2, pp.97-104, 1988.
DOI : 10.1016/0020-0190(88)90036-1

B. Louka and M. Tchuenté, Triangular matrix inversion on systolic arrays, Parallel Computing, vol.14, issue.2, pp.223-228, 1990.
DOI : 10.1016/0167-8191(90)90110-U

J. W. Liu, Computational models and task scheduling for parallel sparse Cholesky factorization, Parallel Computing, vol.3, issue.4, pp.327-342, 1986.
DOI : 10.1016/0167-8191(86)90014-1

D. I. Moldovan, On the Analysis and Synthesis of VLSI Algorithms, IEEE Transactions on Computers, vol.31, issue.11, pp.11-1121, 1982.
DOI : 10.1109/TC.1982.1675929

C. Mongenet, Data compiling for systems of uniform recurrence equations. Parallel Processing Letters, pp.245-257, 1994.

P. Quinton, Automatic synthesis of systolic array from uniform recurrence equations, Proc. IEEE 11th Annual International Conderence on Computer Architecture, pp.208-214, 1984.

P. Quinton and V. V. Dongen, The mapping of linear recurrence equations on regular arrays, Journal of VLSI signal processing systems for signal, image and video technology, vol.88, issue.1, pp.95-113, 1989.
DOI : 10.1007/BF02477176
URL : https://hal.archives-ouvertes.fr/inria-00075466

S. V. Rajopadhye, Synthesizing systolic arrays with control signals from recurrence equations, Distributed Computing, vol.35, issue.2, pp.88-105, 1989.
DOI : 10.1007/BF01558666

S. V. Rajopadhye and R. M. Fujimoto, Synthesizing systolic arrays from recurrence equations, Parallel Computing, vol.14, issue.2, pp.163-189, 1990.
DOI : 10.1016/0167-8191(90)90105-I

T. Risset and Y. Robert, Synthesis of processors arrays for the algebraic path problem: unifying old results and deriving new architectures, Parallel Processing Letters, pp.19-28, 1991.

I. Sakho and M. Tchuente, Methode de conception d'algorithmes paralleles pour reseaux reguliers, Technique et Science Informatiques, vol.8, pp.63-72, 1989.

W. Shang and J. A. Fortes, Time optimal linear schedules for algorithms with uniform dependencies, IEEE Transactions on Computers, vol.40, issue.6, pp.723-742, 1991.
DOI : 10.1109/12.90251

C. T. Djamegni, P. Quinton, S. Rajopadhye, and T. Risset, Derivation of systolic algorithms for the algebraic path problem by recurrence transformations, Parallel Computing, vol.26, issue.11, pp.1429-1445, 2000.
DOI : 10.1016/S0167-8191(00)00039-9

C. T. Djamegni and M. Tchuenté, SCHEDULING OF THE DAG ASSOCIATED WITH PIPELINE INVERSION OF TRIANGULAR MATRICES, Parallel Processing Letters, vol.06, issue.01, pp.13-26, 1996.
DOI : 10.1142/S0129626496000030

C. T. Djamegni and M. Tchuenté, A NEW ALGORITHM FOR DYNAMIC PROGRAMMING ON REGULAR ARRAYS, Parallel Processing Letters, vol.10, issue.01, pp.15-27, 2000.
DOI : 10.1142/S0129626400000044

C. T. Djamegni, Contribution to the Synthesis of Optimal Algorithms for Regular Arrays, Thèse de Doctorat, 1997.

M. Tchuenté, Parallel Computation on regular arrays, 1992.

L. Thiele, Resource constrained scheduling of uniform algorithms, Journal of VLSI signal processing systems for signal, image and video technology, vol.22, issue.3, pp.295-310, 1995.
DOI : 10.1007/BF02120034

Y. Wong and J. M. Delosme, Optimization of processor count for systolic arrays, Research Report, p.697, 1989.

Y. Wong and J. M. Delosme, Space-optimal linear processor allocation for systolic arrays synthesis, Proceedings Sixth International Parallel Processing Symposium, pp.275-282, 1992.
DOI : 10.1109/IPPS.1992.223033

Y. Yaacoby and P. R. Cappelo, BOUNDED BROADCAST IN SYSTOLIC ARRAYS, International Journal of High Speed Computing, vol.06, issue.02, pp.88-101, 1998.
DOI : 10.1142/S0129053394000111