TERAFLUX: Harnessing dataflow in next generation teradevices

Abstract : The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper presents an overview of the research carried out by the TERAFLUX partners and some preliminary results. Our platform comprises 1000+ general purpose cores per chip in order to properly explore the above challenges. An architectural template has been proposed and applications have been ported to the platform. Programming models, compilation tools, and reliability techniques have been developed. The evaluation is carried out by leveraging on modifications of the HP-Labs COTSon simulator.
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Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2014, 38 (8), pp. 976-990. <10.1016/j.micpro.2014.04.001>
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https://hal.inria.fr/hal-00992721
Contributeur : Feng Li <>
Soumis le : lundi 19 mai 2014 - 11:15:59
Dernière modification le : jeudi 29 septembre 2016 - 01:22:38

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Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, et al.. TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2014, 38 (8), pp. 976-990. <10.1016/j.micpro.2014.04.001>. <hal-00992721>

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