| HAL-Inria | Publications, software ... of Inria's scientists |
Conference papers
A new binary floating-point division algorithm and its software implementation on the ST231 processor
Abstract : This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are sufficient to ensure correct rounding. Then we describe the heuristics used to generate such evaluation programs, as well as those used to automatically validate their accuracy. Finally, we propose, for the binary32 format, a complete C implementation of the resulting division algorithm. With the ST200 compiler and compared to previous implementations, the speed-up observed with our approach is by a factor of almost 1.8.
https://hal.inria.fr/hal-00993090
Contributor : Claude-Pierre Jeannerod <>
Submitted on : Monday, May 19, 2014 - 4:01:35 PM
Last modification on : Thursday, November 21, 2019 - 2:26:42 AM
Contributor : Claude-Pierre Jeannerod <>
Submitted on : Monday, May 19, 2014 - 4:01:35 PM
Last modification on : Thursday, November 21, 2019 - 2:26:42 AM
Links full text
