Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces

Abstract : Nowadays, a challenge faced by many developers is the profiling of parallel applications so that they can scale over more and more cores. This is especially critical for embedded systems powered by Multi-Processor System-on-Chip (MPSoC), where ever demanding applications have to run smoothly on numerous cores, each with modest power budget. The reasons for the lack of scalability of parallel applications are numerous, and it can be time consuming for a developer to pinpoint the correct one. In this paper, we propose a fully automatic method which detects the instructions of the code which lead to a lack of scalability. The method is based on data mining techniques exploiting low level execution traces produced by MPSoC simulators. Our experiments show the accuracy of the proposed technique on five different kinds of applications, and how the information reported can be exploited by application developers.
Type de document :
Communication dans un congrès
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, Dresden, Germany, Germany. pp.1-6, 2014
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https://hal.inria.fr/hal-01002685
Contributeur : Fabrice Jouanot <>
Soumis le : vendredi 6 juin 2014 - 15:42:37
Dernière modification le : jeudi 11 janvier 2018 - 06:22:06

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  • HAL Id : hal-01002685, version 1

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Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot. Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, Dresden, Germany, Germany. pp.1-6, 2014. 〈hal-01002685〉

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