Abstract : This chapter presents a real-time FPGA
implementation of a biologically-inspired image enhancement algorithm.
The algorithm compensates for the under/over-exposed image regions,
emerging when High Dynamic Range (HDR) scenes are captured by
contemporary imaging devices. The transformations of the original
algorithm, which are necessary in order to meet the requirements of an
FPGA-based hardware system, are presented in detail. The proposed
implementation, which is synthesized in Altera's Stratix II GX:
EP2SGX130GF1508C5 FPGA device, features pipeline architecture, allowing
the real-time rendering of color video sequences (25fps) with frame
sizes up to 2.5Mpixels.
Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.133-153, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_8〉
https://hal.inria.fr/hal-01054267
Contributeur : Hal Ifip
<>
Soumis le : mardi 5 août 2014 - 17:01:55
Dernière modification le : mercredi 27 décembre 2017 - 14:04:02
Document(s) archivé(s) le : mercredi 26 novembre 2014 - 00:35:36
Vassilios Vonikakis, Chryssanthi Iakovidou, Ioannis Andreadis. Real-Time Biologically-Inspired Image Exposure
Correction. Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.133-153, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_8〉. 〈hal-01054267〉
