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Altera Corporation (Main Headquarters (San Jose)
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
- United States)
Abstract : In this paper we propose the use of Timed Coloured
Petri Nets for the Performance Evaluation of Hardware/Software systems
for DSP applications. Complex systems on chip, composed by hardware and
software parts, are often required to meet strict timing constraints,
both in terms of throughput and latency. However, the verification of
the suitability of a system configuration can usually be performed only
after the integration of the hardware and software components, when
design modifications and optimizations are particularly expensive. This
article proposes a framework to evaluate the performance of HW/SW
systems in which Timed Coloured Petri Nets can be exploited in the early
phases of the design. The framework is tested by modelling the Physical
Uplink Shared Channel (PUSCH) bit-rate receiver portion of 3GPP (3rd
Generation Partnership Project) LTE (Long Term Evolution) standard, the
next generation of 3G wireless systems.
https://hal.inria.fr/hal-01054268 Contributor : Hal IfipConnect in order to contact the contributor Submitted on : Tuesday, August 5, 2014 - 5:01:56 PM Last modification on : Thursday, March 5, 2020 - 5:40:31 PM Long-term archiving on: : Wednesday, November 26, 2014 - 12:35:45 AM
Laura Frigerio, Kellie Marks, Argy Krikelis. Timed Coloured Petri Nets for Performance
Evaluation of DSP Applications: The 3GPP LTE Case Study. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. pp.114-132, ⟨10.1007/978-3-642-12267-5_7⟩. ⟨hal-01054268⟩