J. F. Parker and D. Ray, A 1.6-GHz CMOS PLL with on-chip loop filter, IEEE Journal of Solid-State Circuits, vol.33, issue.3, pp.337-343, 1998.
DOI : 10.1109/4.661199
URL : https://hal.archives-ouvertes.fr/hal-00552683

J. Craninckx and M. S. Steyaert, A fully integrated CMOS DCS-1800 frequency synthesizer, IEEE Journal of Solid-State Circuits, vol.33, issue.12, pp.2054-2065, 1998.
DOI : 10.1109/4.735547

W. Rhee, Design of high-performance CMOS charge pumps in phase-locked loops, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), pp.545-548, 1999.
DOI : 10.1109/ISCAS.1999.780807

H. R. Rategh, H. Samavati, and T. H. Lee, A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver, IEEE Journal of Solid-State Circuits, vol.35, issue.5, pp.780-787, 2000.
DOI : 10.1109/4.841507

W. Rhee, B. S. Song, and A. Ali, A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator, IEEE Journal of Solid-State Circuits, vol.35, issue.10, pp.1453-1460, 2000.
DOI : 10.1109/4.871322

C. Hungand and K. K. , A fully integrated 1.5-5.5-GHz CMOS phase-locked loop, IEEE Journal of Solid-State Circuits, vol.37, issue.4, pp.521-525, 2002.

B. De-muerand and M. S. Steyaert, A CMOS monolithic ????-controlled fractional-N frequency synthesizer for DCS-1800, IEEE Journal of Solid-State Circuits, vol.37, issue.7, pp.835-844, 2002.
DOI : 10.1109/JSSC.2002.1015680

A. L. Loke, R. K. Barnes, T. T. Wee, M. M. Oshima, C. E. Moore et al., A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking, IEEE Journal of Solid-State Circuits, vol.41, issue.8, pp.1894-1907, 2006.
DOI : 10.1109/JSSC.2006.875289

M. H. Perrott, M. D. Trott, and C. G. Sodini, A modeling approach for ??-?? fractional-N frequency synthesizers allowing straightforward noise analysis, IEEE Journal of Solid-State Circuits, vol.37, issue.8, pp.1028-1038, 2002.
DOI : 10.1109/JSSC.2002.800925

K. Shu, E. Sanchez-sinencio, J. Silva-martinez, and S. H. Embabi, A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier, IEEE Journal of Solid-State Circuits, vol.38, issue.6, pp.866-874, 2003.
URL : https://hal.archives-ouvertes.fr/hal-00271377

H. Arora, N. Klemmer, J. C. Morizio, and P. D. Wolf, Enhanced phase noise modeling of fractional-N frequency synthesizers, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.52, issue.2, pp.379-395, 2005.
DOI : 10.1109/TCSI.2004.841594

H. Huh, Y. Koo, K. Lee, Y. Ok, S. Lee et al., Comparison frequency doubling and charge pump matching techniques for dualband delta sigma fractional-N frequency synthesizer, IEEE Journal of Solid-State Circuits, vol.40, issue.11, pp.2228-2236, 2005.

K. Woo, Y. Liu, E. Nam, and D. Ham, Fast-Lock Hybrid PLL Combining Fractional-<formula formulatype="inline"> <tex>$N$</tex></formula> and Integer-<formula formulatype="inline"><tex>$N$</tex> </formula> Modes of Differing Bandwidths, IEEE Journal of Solid-State Circuits, vol.43, issue.2, pp.379-389, 2008.
DOI : 10.1109/JSSC.2007.914281

T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino et al., A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer, IEEE Journal of Solid-State Circuits, vol.43, issue.4, pp.1030-1037, 2008.
DOI : 10.1109/JSSC.2008.917557

A. M. Fahimand and M. I. Elmasry, A low-power CMOS frequency synthesizer design methodology for wireless applications, The International Symposium on Circuits and Systems (ISCAS), pp.115-119, 1999.

S. Cheng, H. Tong, J. S. Martinez, and A. I. Karsilayan, Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.53, issue.9, pp.843-847, 2006.
DOI : 10.1109/TCSII.2006.879100

T. Rapinoja, K. Stadius, and K. Halonen, A low-power phase-locked loop for uwb applications , Analog Integrated Circuits and Signal Processing, pp.95-103, 2007.

R. C. Chang and L. Kuo, A new low-voltage charge pump circuit for PLL, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), pp.701-704, 2000.
DOI : 10.1109/ISCAS.2000.857586

B. N. Rabaey and A. Chandrakasan, Digital Integrated Circuits, A Design Perspective, 2002.

P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, Analysis of Charge-Pump Phase-Locked Loops, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, issue.9, pp.1665-1674, 2004.
DOI : 10.1109/TCSI.2004.834516

M. Johnson and E. Hudson, A variable delay line PLL for CPU-coprocessor synchronization, IEEE Journal of Solid-State Circuits, vol.23, issue.5, pp.1218-1223, 1988.
DOI : 10.1109/4.5947

I. A. Young, J. K. Greason, and K. L. Wong, A PLL clock generator with 5 to 110 MHz of lock range for microprocessors, IEEE Journal of Solid-State Circuits, vol.27, issue.11, pp.1599-1607, 1992.
DOI : 10.1109/4.165341

J. Maneatis, Low-Jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques, ISSCC Digest of Technical Papers, 1996.

M. Soyuer, J. F. Ewen, and H. L. Chuang, A Fully Monolithic 1.25GHz CMOS Frequency Synthesizer, Symposium on VLSI Circuits, Digest of Technical Papers, pp.127-128, 1994.

B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, pp.1-39, 1996.
DOI : 10.1109/9780470545331