M. Nakagawa and . Watanabe, Giga-hertz electrical characteristics of flip-chip BGA package exceeding 2,000 pin counts, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)
DOI : 10.1109/ECTC.2004.1319361

K. H. Yuan and . Pang, Electrical analysis and design of differential pairs used in highspeed flip-chip BGA packages, p.17

J. Westra and P. Groeneveld, Post-placement pin optimization, IEEE Computer Society Annual Symposium on VLSI. 2005, pp.238-243

P. Westra and . Groeneveld, Towards Integration of Quadratic Placement and Pin Assignment, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp.284-286
DOI : 10.1109/ISVLSI.2005.73

X. Xiang, D. F. Tang, and . Wong, An algorithm for integrated pin assignment and buffer planning, Proceedings. 39 th

X. Xiang, D. F. Tang, and . Wong, Min-cost flow-based algorithm for simultaneous pin assignment and routing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22, issue.7, pp.22870-878, 2003.
DOI : 10.1109/TCAD.2003.814258

J. Meister, G. Lienig, and . Thomke, Novel Pin Assignment Algorithms for Components with Very High Pin Counts, Proceedings Design, Automation and Test in Europe, pp.8-837, 2008.

W. Chen, J. Tseng, S. Yan, and . Chen, Printed circuit board routing and package layout codesign, APCCAS, pp.155-158, 2002.

A. Kubo and . Takahashi, A global routing method for 2-layer ball grid array packages, Proceedings of the 2005 international symposium on physical design , ISPD '05, pp.36-43
DOI : 10.1145/1055137.1055146

Y. and W. W. Dai, Pin assignment and routing on a single-layer pin grid array, Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95, pp.203-208, 1995.

. Galil, Efficient algorithms for finding maximum matching in graphs, ACM Computing Surveys, vol.18, issue.1, pp.23-38, 1986.
DOI : 10.1145/6462.6502

N. Gabow, An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs, Journal of the ACM, vol.23, issue.2, pp.221-234
DOI : 10.1145/321941.321942

H. Choi, H. Lee, and . Park, A Three-Data Differential Signaling Over Four Conductors With Pre-Emphasis and Equalization: A CMOS Current Mode Implementation, IEEE Journal of Solid-State Circuits, vol.41, issue.3, pp.633-641, 2006.
DOI : 10.1109/JSSC.2005.864117

A. Sherwani, Algorithms for VLSI Physcial Design Automation, 1998.

P. Westra and . Groeneveld, Towards integration of quadratic placement and pin assignment, VLSI, Proceedings. IEEE Computer Society Annual Symposium on, pp.284-286, 2005.

X. Xiang, M. Tang, and . Wong, Min-cost flow-based algorithm for simultaneous pin assignment and routing Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.22, pp.870-878, 2003.