Physical Design Issues in 3-D Integrated Technologies

Abstract : Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.
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Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.1-21, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_1〉
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Vasilis F. Pavlidis, Eby G. Friedman. Physical Design Issues in 3-D Integrated Technologies. Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.1-21, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_1〉. 〈hal-01054273〉

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