Abstract : Design techniques for three-dimensional (3-D) ICs
considerably lag the significant strides achieved in 3-D manufacturing
technologies. Advanced design methodologies for 2-D circuits are not
sufficient to manage the added complexity caused by the third dimension.
Consequently, design methodologies that efficiently handle the added
complexity and inherent heterogeneity of 3-D circuits are necessary.
These 3-D design methodologies should support robust and reliable 3-D
circuits, while considering different forms of vertical integration,
such as systems-in-package and 3-D ICs with fine grain vertical
interconnections. The techniques described in this chapter address
important physical design issues and fundamental interconnect structures
in the 3-D design process.
https://hal.inria.fr/hal-01054273 Contributor : Hal IfipConnect in order to contact the contributor Submitted on : Tuesday, August 5, 2014 - 5:02:04 PM Last modification on : Thursday, March 5, 2020 - 5:40:30 PM Long-term archiving on: : Wednesday, November 26, 2014 - 12:36:30 AM
Vasilis F. Pavlidis, Eby G. Friedman. Physical Design Issues in 3-D Integrated
Technologies. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. pp.1-21, ⟨10.1007/978-3-642-12267-5_1⟩. ⟨hal-01054273⟩