V. F. Pavlidis, E. G. Friedman, and J. W. Joyner, Semiconductor Industry Association Three Dimensional Integrated Circuit Design Impact of Three-Dimensional Architectures on Interconnects in Gigascale Integration System Level Performance Evaluation of Three-Dimensional Integrated Circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems Accurate Interconnection Lengths in Three- Dimensional Computer Systems Opportunities for Reduced Power Distribution Using Three-Dimensional Integration, Proceedings of the IEEE International Interconnect Technology Conference ICs: A Novel Chip Design Paradigm for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration Proceedings of the IEEE, pp.922-928, 2000.

M. Koyanagi, Future system-on-silicon LSI chips, Proceedings of the IEEE, pp.17-22, 1998.
DOI : 10.1109/40.710867

K. Bernstein, Interconnects in the third dimension, Proceedings of the 44th annual conference on Design automation, DAC '07, pp.562-567, 2007.
DOI : 10.1145/1278480.1278623

R. S. Patti, Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs, Proceedings of the IEEE, vol.94, issue.6, pp.1214-1224, 2006.
DOI : 10.1109/JPROC.2006.873612

D. L. Lewis and H. S. Lee, A Scan-Island Based Design Enabling Pre-Bond Testability in Die-Stacked Microprocessors, Proceedings of the IEEE International Test Conference, pp.1-8, 2007.

J. Cong, J. Wei, and Y. Zhang, A thermal-driven floorplanning algorithm for 3D ICs, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004., pp.306-313, 2004.
DOI : 10.1109/ICCAD.2004.1382591

D. Henry, Low Electrical Resistance Silicon Through Vias: Technology and Characterization, 56th Electronic Components and Technology Conference 2006, pp.1360-1365, 2006.
DOI : 10.1109/ECTC.2006.1645834

P. Garrou, Future ICs Go Vertical Semiconductor International, 2005.

M. Karnezos, 3D packaging: where all technologies come together, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585), pp.64-67, 2004.
DOI : 10.1109/IEMT.2004.1321633

J. Miettinen, M. Mantysalo, K. Kaija, and E. O. Ristolainen, System design issues for 3D system-in-package (SiP), 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), pp.610-615, 2004.
DOI : 10.1109/ECTC.2004.1319401

E. Beyne, The Rise of the 3 rd

V. F. Pavlidis and E. G. Friedman, Interconnect delay minimization through interlayer via placement in 3-D ICs, Proceedings of the 15th ACM Great Lakes symposium on VLSI , GLSVSLI '05, pp.20-25, 2005.
DOI : 10.1145/1057661.1057669

J. A. Burns, A wafer-scale 3-D circuit integration technology, IEEE Transactions on Electron Devices, vol.53, issue.10, pp.2507-2515, 2006.
DOI : 10.1109/TED.2006.882043

C. A. Bower, High Density, Vertical Interconnects for 3-D Integration of Silicon Integrated Circuits, 56th Electronic Components and Technology Conference 2006, pp.399-403, 2006.
DOI : 10.1109/ECTC.2006.1645677

D. M. Jang, Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV), 2007 Proceedings 57th Electronic Components and Technology Conference, pp.847-850, 2007.
DOI : 10.1109/ECTC.2007.373897

I. Savidis and E. G. Friedman, Electrical modeling and characterization of 3-D vias, 2008 IEEE International Symposium on Circuits and Systems, pp.784-787, 2008.
DOI : 10.1109/ISCAS.2008.4541535

R. H. Otten-]-e, C. C. Yong, C. S. Chu, and . Zion, Automatic Floorplan Design Twin Binary Sequences: A Non- Redundant Representation for General Non-Slicing Floorplan, Proceedings of the IEEE/ACM Design Automation Conference, pp.261-267, 1982.

L. Cheng, L. Deng, and D. F. Wong, Floorplanning for 3-D VLSI design, Proceedings of the 2005 conference on Asia South Pacific design automation , ASP-DAC '05, pp.405-411, 2005.
DOI : 10.1145/1120725.1120899

Z. Li, Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.53, issue.12, pp.2637-2646, 2006.
DOI : 10.1109/TCSI.2006.883857

Y. Deng and W. P. Maly, Interconnect characteristics of 2.5-D system integration scheme, Proceedings of the 2001 international symposium on Physical design , ISPD '01, pp.341-345, 2001.
DOI : 10.1145/369691.369763

Z. Li, Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.4, pp.645-658, 2007.
DOI : 10.1109/TCAD.2006.885831

T. Yan, Q. Dong, Y. Takashima, and Y. Kajitani, How does partitioning matter for 3D floorplanning?, Proceedings of the 16th ACM Great Lakes symposium on VLSI , GLSVLSI '06, pp.73-76, 2006.
DOI : 10.1145/1127908.1127928

M. Healy, Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.1, pp.38-52, 2007.
DOI : 10.1109/TCAD.2006.883925

W. Lo, An Innovative Chip-to-Wafer and Wafer-to-Wafer Stacking, Proceedings of the IEEE International Electronic Components and Technology Conference, pp.409-414, 2006.

B. Goplen and S. Sapatnekar, Placement of thermal vias in 3-D ICs using various thermal objectives, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.4, pp.692-709, 2006.
DOI : 10.1109/TCAD.2006.870069

S. T. Obenaus and T. H. Szymanski, Gravity, ACM Transactions on Design Automation of Electronic Systems, vol.8, issue.3, pp.298-315, 2003.
DOI : 10.1145/785411.785413

A. Harter, Three-Dimensional Integrated Circuit Layout, 1991.
DOI : 10.1017/CBO9780511666384

I. Kaya, M. Olbrich, and E. Barke, 3-D placement considering vertical interconnects, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings., pp.257-258, 2003.
DOI : 10.1109/SOC.2003.1241509

W. R. Davis, Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design and Test of Computers, vol.22, issue.6, 2005.
DOI : 10.1109/MDT.2005.136

H. Eisenmann and F. M. Johannnes, Generic global placement and floorplanning, Proceedings of the 35th annual conference on Design automation conference , DAC '98, pp.269-274, 1998.
DOI : 10.1145/277044.277119

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.32.1891

B. Goplen and S. Sapatnekar, Efficient thermal placement of standard cells in 3D ICs using a force directed approach, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), pp.86-89, 2003.
DOI : 10.1109/ICCAD.2003.1257591

R. J. Enbody, G. Lynn, and K. H. Tan, Routing the 3-D chip, Proceedings of the 28th conference on ACM/IEEE design automation conference , DAC '91, pp.132-137, 1991.
DOI : 10.1145/127601.127644

C. C. Tong and C. Wu, Routing in a three-dimensional chip, IEEE Transactions on Computers, vol.44, issue.1, pp.106-117, 1995.
DOI : 10.1109/12.368006

J. Minz and S. K. Lim, Block-level 3-D Global Routing With an Application to 3-D Packaging, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.10, pp.2248-2257, 2006.
DOI : 10.1109/TCAD.2005.860952

T. Ohtsuki, Advances in CAD for VLSI, 1986.

J. Cong, M. Xie, and Y. Zhang, An Enhanced Multilevel Routing System, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.51-58, 2002.

J. Cong and Y. Zhang, Thermal-driven multilevel routing for 3-D ICs, Proceedings of the 2005 conference on Asia South Pacific design automation , ASP-DAC '05, pp.121-126, 2005.
DOI : 10.1145/1120725.1120787

V. F. Pavlidis and E. G. Friedman, Timing-driven via placement heuristics for three-dimensional ICs, Integration, the VLSI Journal, vol.41, issue.4, pp.489-508, 2008.
DOI : 10.1016/j.vlsi.2007.11.002

K. D. Boese, Fidelity and near-optimality of Elmore-based routing constructions, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93, pp.81-84, 1993.
DOI : 10.1109/ICCD.1993.393400

J. Löfberg, YALMIP : a toolbox for modeling and optimization in MATLAB, 2004 IEEE International Conference on Robotics and Automation (IEEE Cat. No.04CH37508), pp.284-289, 2004.
DOI : 10.1109/CACSD.2004.1393890

E. G. Friedman, Clock Distribution Networks in VLSI Circuits and Systems, 1995.

E. G. Friedman, Clock distribution networks in synchronous digital integrated circuits, Proceedings of the IEEE, vol.89, issue.5, pp.665-692, 2001.
DOI : 10.1109/5.929649

T. Xanthopoulos, The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), pp.402-402, 2001.
DOI : 10.1109/ISSCC.2001.912693

C. Punty and L. Gal, Optimum Tapered Buffer, IEEE Journal of Solid-State Circuits, vol.27, issue.1, pp.1005-1008, 1992.

V. F. Pavlidis, I. Savidis, and E. G. Friedman, Clock Distribution Networks for 3-D Integrated Circuits, Proceedings of the IEEE International Conference on Custom Integrated Circuits, pp.651-654, 2008.

V. F. Pavlidis, I. Savidis, and E. G. Friedman, Clock distribution architectures for 3-D SOI integrated circuits, 2008 IEEE International SOI Conference, pp.111-112, 2008.
DOI : 10.1109/SOI.2008.4656319

L. Benini and G. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921

S. Kumar, A network on chip architecture and design methodology, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, pp.105-112, 2002.
DOI : 10.1109/ISVLSI.2002.1016885

F. Li, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, Proceedings of the IEEE International Symposium on Computer Architecture, pp.130-142, 2006.
DOI : 10.1145/1150019.1136497

V. F. Pavlidis and E. G. Friedman, 3-D Topologies for Networks-on-Chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1081-1090, 2007.