Skip to Main content Skip to Navigation
Conference papers

Timing Error Detection and Correction by Time Dilation

Abstract : Timing failures in high complexity - high frequency integrated circuits, which are mainly caused by test escapes and environmental as well as operating conditions, are a real concern in nanometer technologies. The Time Dilation design technique supports both on-line (concurrent) error detection/correction and off-line scan testing. It is based on a new scan Flip-Flop and provides multiple error detection and correction at the minimum penalty of one clock cycle delay at the normal circuit operation for each error correction. No extra memory elements are required, like in earlier design approaches in the open literature, reducing drastically the silicon area overhead, while the performance degradation is negligible since no extra circuitry is inserted in the critical paths of a design.
Document type :
Conference papers
Complete list of metadata

Cited literature [12 references]  Display  Hide  Download

https://hal.inria.fr/hal-01054274
Contributor : Hal Ifip <>
Submitted on : Tuesday, August 5, 2014 - 5:02:05 PM
Last modification on : Thursday, March 5, 2020 - 5:40:22 PM
Long-term archiving on: : Wednesday, November 26, 2014 - 12:36:39 AM

File

03130293.pdf
Files produced by the author(s)

Licence


Distributed under a Creative Commons Attribution 4.0 International License

Identifiers

Citation

Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos. Timing Error Detection and Correction by Time Dilation. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. pp.271-285, ⟨10.1007/978-3-642-12267-5_15⟩. ⟨hal-01054274⟩

Share

Metrics

Record views

364

Files downloads

1179