Timing Error Detection and Correction by Time Dilation

Abstract : Timing failures in high complexity - high frequency integrated circuits, which are mainly caused by test escapes and environmental as well as operating conditions, are a real concern in nanometer technologies. The Time Dilation design technique supports both on-line (concurrent) error detection/correction and off-line scan testing. It is based on a new scan Flip-Flop and provides multiple error detection and correction at the minimum penalty of one clock cycle delay at the normal circuit operation for each error correction. No extra memory elements are required, like in earlier design approaches in the open literature, reducing drastically the silicon area overhead, while the performance degradation is negligible since no extra circuitry is inserted in the critical paths of a design.
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Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.271-285, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_15〉
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Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos. Timing Error Detection and Correction by Time Dilation. Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.271-285, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_15〉. 〈hal-01054274〉

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