S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, Robust system design with built-in soft-error resilience, Computer, vol.38, issue.2, pp.43-52, 2005.
DOI : 10.1109/MC.2005.70

T. Austin, D. Blaauw, T. Mudge, and K. Flautner, Making typical silicon matter with Razor, Computer, vol.37, issue.3, pp.57-65, 2004.
DOI : 10.1109/MC.2004.1274005

M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra, Circuit Failure Prediction and Its Application to Transistor Aging, 25th IEEE VLSI Test Symmposium (VTS'07), pp.277-284, 2007.
DOI : 10.1109/VTS.2007.22

M. Nicolaidis and Y. Zorian, On-line Testing for VLSI???A Compendium of Approaches, Journal of Electronic Testing: Theory and Applications, vol.12, issue.12, pp.7-20, 1998.
DOI : 10.1007/978-1-4757-6069-9_1

URL : https://hal.archives-ouvertes.fr/hal-00013854

C. Metra, R. Degiampietro, M. Favalli, and B. Ricco, Concurrent Detection and Diagnosis Scheme for Transient, Delay and Crosstalk Faults, IEEE International On-Line Testing Workshop, pp.66-70, 1999.

Y. Tsiatouhas and T. , Haniotakis, A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing, IEEE Symposium on Design for Testability of VLSI Systems, pp.95-100, 1999.

L. Anghel and M. Nicolaidis, Cost Reduction and Evaluation of Temporary Faults Detecting Technique, Europe Conference, pp.591-598, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00013756

S. Matakias, Y. Tsiatouhas, A. Arapoyanni, and T. , A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs, Journal of Electronic Testing, vol.20, issue.5, pp.523-531, 2004.
DOI : 10.1023/B:JETT.0000042516.12841.36

M. Nicolaidis, Time redundancy based soft-error tolerance to rescue nanometer technologies, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.86-94, 1999.
DOI : 10.1109/VTEST.1999.766651

URL : https://hal.archives-ouvertes.fr/hal-00013764

R. F. Sproull, I. E. Sutherland, and C. E. Molnar, The counterflow pipeline processor architecture, IEEE Design & Test of Computers, vol.11, issue.3, pp.48-59, 1994.
DOI : 10.1109/MDT.1994.303847

A. Floros, Y. Tsiatouhas, A. Arapoyanni, and T. , Haniotakis, A Pipeline Architecture Incorporating a Low- Cost Error Detection and Correction Mechanism, IEEE International Conference on Electronics, Circuits and Systems, pp.692-695, 2006.

A. Floros, Y. Tsiatouhas, and X. Kavousianos, The Time Dilation Scan Architecture for Timing Error Detection and Correction, IEEE International Conference on Very Large Scale Integration, pp.569-574, 2008.