Time Efficient Dual-Field Unit for Cryptography-Related Processing

Abstract : Computational demanding public key cryptographic algorithms, such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (EC) cryptosystems, are critically dependent on modular multiplication for their performance. Modular multiplication used in cryptography may be performed in two different algebraic structures, namely GF(N) and GF(2n), which normally require distinct hardware solutions for speeding up performance. For both fields, Montgomery multiplication is the most widely adopted solution, as it enables efficient hardware implementations, provided that a slightly modified definition of modular multiplication is adopted. In this paper we propose a novel unified architecture for parallel Montgomery multiplication supporting both GF(N) and GF(2n) finite field operations, which are critical for RSA ad ECC public key cryptosystems. The hardware scheme interleaves multiplication and modulo reduction. Furthermore, it relies on a modified Booth recoding scheme for the multiplicand and a radix-4 scheme for the modulus, enabling reduced time delays even for moderately large operand widths. In addition, we present a pipelined architecture based on the parallel blocks previously introduced, enabling very low clock counts and high throughput levels for long operands used in cryptographic applications. Experimental results, based on 0.18 μm CMOS technology, prove the effectiveness of the proposed techniques, and outperform the best results previously presented in the technical literature.
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Communication dans un congrès
Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.191-210, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_11〉
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Alessandro Cilardo, Nicola Mazzocca. Time Efficient Dual-Field Unit for Cryptography-Related Processing. Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.191-210, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_11〉. 〈hal-01054277〉

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