RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors

Abstract : Increasingly, embedded systems designers tend to use Application Specific Instruction Set Processors (ASIPs) during the design of application specific systems. However, one of the design metrics of embedded systems is the time to market of a product, which includes the design time of an embedded processor, is an important consideration in the deployment of ASIPs. While the design time of an ASIP is very short compared to an ASIC it is longer than when using a general purpose processor. There exist a number of tools which expedite this design process, and they could be divided into two: first, tools that automatically generate HDL descriptions of the processor for both simulation and synthesis; and second, tools that generate instruction set simulators for the simulation of the hardware models. While the first one is useful to measure the critical path of the design, die area, etc. they are extremely slow for simulating real world software applications. At the same time, the instruction set simulators are fast for simulating real world software applications, but they fail to provide information so readily available from the HDL models. The framework presented in this paper, RACE, addresses this issue by integrating an automatic HDL generator with a well-known instruction set simulator. Therefore, embedded systems designers who use our RACE framework will have the benefits of both a fast instruction set simulation and rapid hardware synthesis at the same time.
Type de document :
Communication dans un congrès
Mike Hinchey; Bernd Kleinjohann; Lisa Kleinjohann; Peter A. Lindsay; Franz J. Rammig; Jon Timmis; Marilyn Wolf. 7th IFIP TC 10 Working Conference on Distributed, Parallel and Biologically Inspired Systems (DIPES) / 3rd IFIP TC 10 International Conference on Biologically-Inspired Collaborative Computing (BICC) / Held as Part of World Computer Congress (WCC) , Sep 2010, Brisbane, Australia. Springer, IFIP Advances in Information and Communication Technology, AICT-329, pp.137-144, 2010, Distributed, Parallel and Biologically Inspired Systems. 〈10.1007/978-3-642-15234-4_14〉
Liste complète des métadonnées

https://hal.inria.fr/hal-01054480
Contributeur : Hal Ifip <>
Soumis le : jeudi 7 août 2014 - 11:16:53
Dernière modification le : lundi 15 janvier 2018 - 12:20:02
Document(s) archivé(s) le : mardi 11 avril 2017 - 19:03:54

Fichier

final_012.pdf
Fichiers produits par l'(les) auteur(s)

Licence


Distributed under a Creative Commons Paternité 4.0 International License

Identifiants

Citation

Roshan Ragel, Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran. RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. Mike Hinchey; Bernd Kleinjohann; Lisa Kleinjohann; Peter A. Lindsay; Franz J. Rammig; Jon Timmis; Marilyn Wolf. 7th IFIP TC 10 Working Conference on Distributed, Parallel and Biologically Inspired Systems (DIPES) / 3rd IFIP TC 10 International Conference on Biologically-Inspired Collaborative Computing (BICC) / Held as Part of World Computer Congress (WCC) , Sep 2010, Brisbane, Australia. Springer, IFIP Advances in Information and Communication Technology, AICT-329, pp.137-144, 2010, Distributed, Parallel and Biologically Inspired Systems. 〈10.1007/978-3-642-15234-4_14〉. 〈hal-01054480〉

Partager

Métriques

Consultations de la notice

200

Téléchargements de fichiers

74