Abstract : Network-on-Chip (NoC) has emerged as a very
promising paradigm for designing scalable communication architecture for
Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth
requirements between the cores of an SoC for a certain set of running
applications may be highly sub-optimal for another set of applications.
In this context, methods that can lead to versatility enhancements of
initial NoC designs to changing working conditions, imposed by variable
sets of executed real-life applications at each moment in time, are very
important for designing competitive NoCs in industrial SoCs. In this
work, we present a run-time reconfigurable NoC framework based on the
partial dynamic reconfiguration capabilities of Field-Programmable Gate
Arrays (FPGAs). This new NoC framework can dynamically create/delete
express lines between SoC components (implementing dynamically
circuit-switching channels) and perform run-time NoC topology and
routing-table reconfigurations to handle interconnection congestion,
with a very limited performance overhead. Moreover, we show in our
experimental results that the addition of these dynamic reconfiguration
capabilities into basic NoCs using our framework only implies a very
limited area overhead (around 10% on average) with respect to the
initial NoC designs; thus, it can bring great benefits when compared to
traditional non-reconfigurable NoC design approaches for worst-case
bandwidth requirements in SoCs with many possible sets of running
applications.
Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, VLSI-SoC: Design Methodologies for SoC and SiP, AICT-313, pp.232-250, 2010, IFIP Advances in Information and Communication Technology. 〈10.1007/978-3-642-12267-5_13〉
https://hal.inria.fr/hal-01054544
Contributeur : Hal Ifip
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Soumis le : jeudi 7 août 2014 - 11:41:25
Dernière modification le : mercredi 28 mars 2018 - 14:38:13
Document(s) archivé(s) le : mercredi 26 novembre 2014 - 01:40:23
Vincenzo Rana, David Atienza, Marco Domenico Santambrogio, Donatella Sciuto, Giovanni Micheli. A Reconfigurable Network-on-Chip Architecture
for Optimal Multi-Processor SoC Communication. Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, VLSI-SoC: Design Methodologies for SoC and SiP, AICT-313, pp.232-250, 2010, IFIP Advances in Information and Communication Technology. 〈10.1007/978-3-642-12267-5_13〉. 〈hal-01054544〉
