K. Goossens, J. Dielissen, and A. Radulescu, The AEthereal network on chip: Concepts, architectures, and implementations, IEEE Design and Test of Computers, vol.22, issue.5, pp.21-31, 2005.

Y. Wang, K. Zhou, Z. Lu, and H. Yang, Dynamic TDM virtual circuit implementation for NoC, APCCAS 2008, 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008.
DOI : 10.1109/APCCAS.2008.4746325

Z. Lu and A. Jantsch, Slot Allocation for TDM Virtual-Circuit Configuration for Network-on-Chip, Proceedings of the 2007 International Conference on Computer- Aided Design (ICCAD'07), IEEE Conferences, 2007.

J. Y. Boudec and P. Thiran, Network Calculus A Theory of Deterministic Queuing Systems for the Internet, LNCS, vol.2050, 2004.

L. Tong, Z. Lu, and H. Zhang, Exploration of Slot Allocation for On-Chip TDM Virtual Circuits. The 12th EUROMICRO Conference on Digital System Design, IEEE Conferences, 2009.

D. Stiliadis and A. Varma, Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms, 1995.

M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.890-895, 2004.
DOI : 10.1109/DATE.2004.1269001

M. Coenen, S. Murali, A. Radulescu, K. Goossens, and G. Micheli, A buffer-sizing algorithm for networks on chip using TDMA and creditbased end-to-end flow control, Proceedings of International Conference on Hardware/Software Codesign and System Synthesis, 2006.

Z. Lu and A. Jantsch, TDM Virtual-Circuit Configuration for Network-on-Chip, Proceedings of the 2007 International Conference on Computer-Aided Design (IC- CAD'07), IEEE Conferences, 2007.
DOI : 10.1109/TVLSI.2008.2000673
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.141.7401

Z. Lu, D. Brachos, and A. Jantsch, A Flow Regulator for On-Chip Communication, The 22nd IEEE International SoC Conference (SoCC'09, IEEE Conferences, 2009.