Skip to Main content Skip to Navigation
Conference papers

Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors

Abstract : DRAM row buffer conflicts can increase the memory access latency significantly for single-threaded applications. In a chip multiprocessor system, multiple applications competing for DRAM will suffer additional row buffer conflicts due to interthread interference. This paper presents a new hardware and software cooperative DRAM bank partitioning method that combines page coloring and XOR cache mapping to evaluate the benefit potential of reducing interthread interference. Using SPECfp2000 as our benchmarks, our simulation results show that our scheme can boost the performance of the most benchmark combinations tested, with the speedups of up to 13%, 14% and 8.06% observed for two cores (with 16 banks), two cores (with 32 banks) and four cores (with 32 banks).
Document type :
Conference papers
Complete list of metadata

Cited literature [18 references]  Display  Hide  Download
Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Monday, August 11, 2014 - 9:16:03 AM
Last modification on : Monday, January 15, 2018 - 12:20:02 PM
Long-term archiving on: : Wednesday, November 26, 2014 - 9:36:33 PM


Files produced by the author(s)


Distributed under a Creative Commons Attribution 4.0 International License



Wei Mi, Xiaobing Feng, Jingling Xue, Yaocang Jia. Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors. IFIP International Conference on Network and Parallel Computing (NPC), Sep 2010, Zhengzhou, China. pp.329-343, ⟨10.1007/978-3-642-15672-4_28⟩. ⟨hal-01054975⟩



Record views


Files downloads