M. Abadi, Secrecy by typing in security protocols, Journal of the ACM, vol.46, issue.5, pp.749-786, 1999.
DOI : 10.1145/324133.324266

F. A. Administration, Federal Register, 2008.

S. Altmeyer, C. Maiza, and J. Reineke, Resilience analysis: tightening the CRPD bound for set-associative caches, LCTES, pp.153-162, 2010.

S. Andova, C. Cremers, K. Gjøsteen, S. Mauw, S. F. Mjølsnes et al., A framework for compositional verification of security protocols, Information and Computation, vol.206, issue.2-4, pp.2-4425, 2008.
DOI : 10.1016/j.ic.2007.07.002

M. Backes, A. Cortesi, R. Focardi, and M. Maffei, A calculus of challenges and responses, Proceedings of the 2007 ACM workshop on Formal methods in security engineering , FMSE '07, pp.101-116, 2007.
DOI : 10.1145/1314436.1314444

M. Backes, A. Cortesi, and M. Maffei, Causality-based abstraction of multiplicity in cryptographic protocols, Proc. 20th IEEE Symposium on Computer Security Foundations (CSF), pp.355-369, 2007.

M. Backes, C. Hrit¸cuhrit¸cu, and M. Maffei, Type-checking zero-knowledge, Proceedings of the 15th ACM conference on Computer and communications security, CCS '08, pp.357-370, 2008.
DOI : 10.1145/1455770.1455816

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.305.1127

G. Barthe, D. Pichardie, and T. Rezk, A certified lightweight non-interference java bytecode verifier, Proc. 16th European Symposium on Programming (ESOP), Lecture Notes in Computer Science, pp.125-140, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00915189

J. Bengtson, K. Bhargavan, C. Fournet, A. D. Gordon, and S. Maffeis, Refinement types for secure implementations, CSF '08: Proceedings of the 2009 21st IEEE Computer Security Foundations Symposium, pp.17-32, 2008.
URL : https://hal.archives-ouvertes.fr/hal-01294973

K. Bhargavan, C. Fournet, A. D. Gordon, and S. Tse, Verified interoperable implementations of security protocols, Proc. 19th IEEE Computer Security Foundations Workshop (CSFW), pp.139-152, 2006.

B. Blanchet, An efficient cryptographic protocol verifier based on prolog rules, Proceedings. 14th IEEE Computer Security Foundations Workshop, 2001., pp.82-96, 2001.
DOI : 10.1109/CSFW.2001.930138

C. Bodei, M. Buchholtz, P. Degano, F. Nielson, and H. R. Nielson, Static validation of security protocols, Journal of Computer Security, vol.13, issue.3, pp.347-390, 2005.
DOI : 10.3233/JCS-2005-13302

Y. Boichut and T. Genet, Feasible Trace Reconstruction for Rewriting Approximations, Term Rewriting and Applications, 17th International Conference, pp.123-135, 2006.
DOI : 10.1007/11805618_10

URL : https://hal.archives-ouvertes.fr/hal-00463426

M. Bugliesi, R. Focardi, and M. Maffei, Dynamic types for authentication*, Journal of Computer Security, vol.15, issue.6, pp.563-617, 2007.
DOI : 10.3233/JCS-2007-15602

URL : http://doi.org/10.3233/jcs-2007-15602

C. Burguiere, D. Grund, J. Reineke, R. Wilhelm, C. Cullmann et al., Predictability considerations in the design of multicore embedded systems, Embedded Real Time Software and Systems (ERTSS), 2010.

S. V. Campos, S. Vale, A. Campos, M. Gerais, B. Horizonte et al., Analysis and verification of real-time systems using quantitative symbolic algorithms, International Journal on Software Tools for Technology Transfer (STTT), vol.2, issue.3, pp.260-269, 1999.
DOI : 10.1007/s100090050033

S. Chaki and A. Datta, ASPIER: An Automated Framework for Verifying Security Protocol Implementations, 2009 22nd IEEE Computer Security Foundations Symposium, pp.172-185, 2009.
DOI : 10.1109/CSF.2009.20

V. Cortier and S. Delaune, Safely composing security protocols. Formal Methods in System and Design, pp.1-36, 2009.
DOI : 10.1007/978-3-540-77050-3_29

URL : https://hal.archives-ouvertes.fr/inria-00157889

A. Datta, A. Derek, J. Mitchell, and A. Roy, Protocol Composition Logic (PCL), Electronic Notes in Theoretical Computer Science, vol.172, pp.311-358, 2007.
DOI : 10.1016/j.entcs.2007.02.012

URL : http://doi.org/10.1016/j.entcs.2007.02.012

S. A. Edwards and E. A. Lee, The case for the precision timed (pret) machine, DAC, pp.264-265, 2007.

C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt et al., WCET Determination for a Real-Life Processor, Embedded Software (EMSOFT 2001), volume 2211 of Lecture Notes in Computer Science, pp.469-485, 2001.

S. Genaim and F. Spoto, Information Flow Analysis for Java Bytecode, Verification , Model Checking, and Abstract Interpretation, pp.346-362, 2005.
DOI : 10.1007/978-3-540-30579-8_23

T. Genet and V. Tong, Reachability Analysis of Term Rewriting Systems with Timbuk, Proc. Artificial Intelligence on Logic for Programming (LPAR '01), pp.695-706, 2001.
DOI : 10.1007/3-540-45653-8_48

URL : https://hal.archives-ouvertes.fr/inria-00072321

A. D. Gordon and A. Jeffrey, Types and effects for asymmetric cryptographic protocols, Journal of Computer Security, vol.12, issue.3-4, pp.435-484, 2004.
DOI : 10.3233/JCS-2004-123-406

URL : http://doi.org/10.3233/jcs-2004-123-406

J. Goubault-larrecq and F. Parrennes, Cryptographic Protocol Analysis on Real C Code, Proc. 6th International Conference on Verification, Model Checking and Abstract Interpretation (VMCAI'05), pp.363-379, 2005.
DOI : 10.1007/978-3-540-30579-8_24

J. D. Guttman and F. J. Thayer, Protocol independence through disjoint encryption, Proceedings 13th IEEE Computer Security Foundations Workshop. CSFW-13, pp.24-34, 2000.
DOI : 10.1109/CSFW.2000.856923

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.298.3042

D. Halperin, T. S. Heydt-benjamin, B. Ransford, S. S. Clark, B. Defend et al., Pacemakers and Implantable Cardiac Defibrillators: Software Radio Attacks and Zero-Power Defenses, 2008 IEEE Symposium on Security and Privacy (sp 2008), pp.129-142, 2008.
DOI : 10.1109/SP.2008.31

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.453.4132

R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, The influence of processor architecture on the design and the results of WCET tools, IEEE Proceedings on Real-Time Systems, pp.911038-1054, 2003.
DOI : 10.1109/JPROC.2003.814618

W. Kim, J. Kim, and S. Min, A dynamic voltage scaling algorithm for dynamicpriority hard real-time systems using slack time analysis, DATE '02: Proceedings of the conference on Design, automation and test in Europe, p.788, 2002.

P. Koopman, Embedded system security, Computer, vol.37, issue.7, pp.95-97, 2004.
DOI : 10.1109/MC.2004.52

B. Köpf and D. A. Basin, An information-theoretic model for adaptive side-channel attacks, Proceedings of the 14th ACM conference on Computer and communications security , CCS '07, pp.286-296, 2007.
DOI : 10.1145/1315245.1315282

C. Lee, J. Han, Y. Seo, S. Min, R. Ha et al., Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling, Proceedings of the IEEE Real-Time Systems Symposium, 1996.

S. Lee, C. Lee, L. M. , S. L. Min, and C. S. Kim, Limited preemptible scheduling to embrace cache memory in real-time systems, Proceedings of the ACM SIGPLAN LCTES'98 Workshop on Languages, Compilers and Tools for Embedded Systems, pp.51-64, 1998.
DOI : 10.1007/BFb0057780

S. Lim, Y. H. Bae, G. T. Jang, B. Rhee, S. L. Min et al., An accurate worst case timing analysis for RISC processors, IEEE Transactions on Software Engineering, vol.21, issue.7, pp.593-604, 1995.

T. Lundquist and P. Stenström, Timing Anomalies in Dynamically Scheduled Microprocessors, 20th IEEE Real-Time Systems Symposium, 1999.

M. Maffei, Tags for Multi-Protocol Authentication, Proc. 2nd International Workshop on Security Issues in Coordination Models, Languages, and Systems Electronic Notes on Theoretical Computer Science, pp.55-63, 2004.
DOI : 10.1016/j.entcs.2004.11.042

J. Mische, I. Guliashvili, S. Uhrig, and T. Ungerer, How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT, Lecture Notes in Computer Science, vol.5974, pp.2-14, 2010.
DOI : 10.1007/978-3-642-11950-7_2

M. Paolieri, E. Quiones, F. J. Cazorla, G. Bernat, and M. Valero, Hardware support for wcet analysis of hrt multicore systems, The 36th International Symposium on Computer Architecture, 2009.

P. Puschner and C. Koza, Calculating the maximum execution time of real-time programs. Real-Time Systems, pp.159-176, 1989.

M. Raya and J. Hubaux, The security of vehicular ad hoc networks, Proceedings of the 3rd ACM workshop on Security of ad hoc and sensor networks , SASN '05, pp.11-21, 2005.
DOI : 10.1145/1102219.1102223

J. Reineke, Caches in WCET Analysis, 2008.

J. Reineke, D. Grund, C. Berg, and R. Wilhelm, Timing Predictability of Cache Replacement Policies. Real-Time Systems, pp.99-122, 2007.

J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian et al., A definition and classification of timing anomalies, Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2006.

T. W. Reps and G. Balakrishnan, Improved Memory-Access Analysis for x86 Executables, Lecture Notes in Computer Science, vol.4959, pp.16-35, 2008.
DOI : 10.1007/978-3-540-78791-4_2

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.102.1806

K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg, FAST, ACM Transactions on Embedded Computing Systems, vol.5, issue.1, pp.200-224, 2006.
DOI : 10.1145/1132357.1132364

A. C. Shaw, Reasoning about time in higher-level language software, IEEE Transactions on Software Engineering, vol.15, issue.7, pp.875-889, 1989.
DOI : 10.1109/32.29487

J. A. Stankovic and K. Ramamritham, Editorial: What is predictability for realtime systems? Real-Time Systems, pp.247-254, 1990.

S. Thesing, J. Souyris, R. Heckmann, F. Randimbivololona, M. Langenbach et al., An Abstract Interpretation-Based Timing Validation of Hard Real-Time Avionics Software Systems, Proceedings of the Performance and Dependability Symposium, 2003.

C. B. Watkins and R. Walter, Transitioning from federated avionics architectures to Integrated Modular Avionics, 2007 IEEE/AIAA 26th Digital Avionics Systems Conference, 2007.
DOI : 10.1109/DASC.2007.4391842

R. Wilhelm, D. Grund, J. Reineke, M. Pister, M. Schlickling et al., Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.7, pp.966-978, 2009.
DOI : 10.1109/TCAD.2009.2013287

J. C. Wray, An analysis of covert timing channels. Security and Privacy, IEEE Symposium on, issue.2, 1991.