M. Alt, C. Ferdinand, F. Martin, and R. Wilhelm, Cache behavior prediction by abstract interpretation, Static Analysis Symposium, 1996.
DOI : 10.1007/3-540-61739-6_33

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.69.6198

C. Ballabriga and H. Cassé, Improving the First-Miss Computation in Set-Associative Instruction Caches, 2008 Euromicro Conference on Real-Time Systems, 2008.
DOI : 10.1109/ECRTS.2008.34

I. Bate and R. Reutemann, Efficient Integration of Bimodal Branch Prediction and Pipeline Analysis, 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'05), 2005.
DOI : 10.1109/RTCSA.2005.41

G. Bernat, A. Colin, and S. Petters, pWCET a Toolset for automatic Worst-Case Execution Time Analysis of Real-Time Embedded Programs, 2003.

R. Bourgade, C. Ballabriga, H. Cassé, C. Rochange, and P. Sainrat, Accurate analysis of memory latencies for WCET estimation, Intl Conference on Real-Time and Network Systems, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00336530

C. Burguì-ere and C. Rochange, On the Complexity of Modelling Dynamic Branch Predictors when Computing Worst-Case Execution Times, ERCIM/DECOS Workshop on Dependable Embedded Systems, 2007.

A. Colin and I. Puaut, Worst Case Execution Time Analysis for a Processor with Branch Prediction. Real-Time Systems Journal, 2000.

A. Colin and I. Puaut, A modular and retargetable framework for tree-based WCET analysis, Proceedings 13th Euromicro Conference on Real-Time Systems, 2001.
DOI : 10.1109/EMRTS.2001.933995

P. Cousot and R. Cousot, Abstract Interpretation -A Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints, ACM Symp. on Principles of Programming Languages, 1977.

D. Michiel, M. Bonenfant, A. Cassé, H. Sainrat, and P. , Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2008.
DOI : 10.1109/RTCSA.2008.53

C. Ferdinand, F. Martin, and R. Wilhelm, Applying compiler techniques to cache behavior prediction, ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, 1997.

D. Hardy and I. Puaut, WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches, 2008 Real-Time Systems Symposium, 2008.
DOI : 10.1109/RTSS.2008.10

C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon, Bounding pipeline and instruction cache performance, IEEE Transactions on Computers, vol.48, issue.1, 1999.
DOI : 10.1109/12.743411

R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, The influence of processor architecture on the design and the results of WCET tools, Proceedings of the IEEE, 2003.
DOI : 10.1109/JPROC.2003.814618

Y. Huang, L. Peng, C. Wu, Y. Kashnikov, J. Renneke et al., Transforming GCC into a research-friendly environment -plugins for optimization tuning and reordering, function cloning and program instrumentation, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00451106

Y. Li and S. Malik, Performance Analysis of Embedded Software using Implicit Path Enumeration, Workshop on Languages, Compilers, and Tools for Real-time Systems, 1995.

X. Li, A. Roychoudhury, and T. Mitra, Modeling out-of-order processors for WCET analysis, Real-Time Systems, vol.5, issue.4, 2006.
DOI : 10.1007/s11241-006-9205-5

S. Lim, Y. H. Bae, G. T. Jang, B. Rhee, S. L. Min et al., An accurate worst case timing analysis technique for RISC processors, IEEE Real-Time Systems Symposium, 1994.

S. Lim, J. Kim, and S. Min, A worst case timing analysis technique for optimized programs, International Conference on Real-Time Computing Systems and Applications, 1998.

M. Paolieri, E. Quiones, F. Cazorla, G. Bernat, and M. Valero, Hardware Support for WCET Analysis of HRT Multicore Systems, Int'l Symposium on Computer Architecture, 2009.

P. Puschner and A. Burns, Writing temporally predictable code, Proceedings of the Seventh IEEE International Workshop on Object-Oriented Real-Time Dependable Systems. (WORDS 2002), 2002.
DOI : 10.1109/WORDS.2002.1000040

T. Ratsiambahotra, H. Cassé, and P. Sainrat, A Versatile Generator of Instruction Set Simulators and Disassemblers, 2009.

C. Rochange and P. Sainrat, A Context-Parameterized Model for Static Analysis of Execution Times, Transactions on High-Performance Embedded Architectures and Compilers, 2007.
DOI : 10.1007/978-3-642-00904-4_12

R. Sen and Y. Srikant, WCET estimation for executables in the presence of data caches, Proceedings of the 7th ACM & IEEE international conference on Embedded software , EMSOFT '07, 2007.
DOI : 10.1145/1289927.1289960

J. Staschulat and R. Ernst, Worst case timing analysis of input dependent data cache behavior, 18th Euromicro Conference on Real-Time Systems (ECRTS'06), 2006.
DOI : 10.1109/ECRTS.2006.33

H. Theiling and C. Ferdinand, Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279), 1998.
DOI : 10.1109/REAL.1998.739739

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., Stenström: The Worst-Case Execution Time Problem -Overview of Methods and Survey of Tools Open source (Mixed-Integer) Linear Programming system, ACM Transactions on Embedded Computing Systems, vol.7, issue.32, 2008.